Datasheet
151
ATmega323(L)
1457E–11/01
Figure 81. Port D Schematic Diagram (Pins PD2 and PD3)
Figure 82. Port D Schematic Diagram (Pins PD4 and PD5)
PUD
WP:
WD:
RL:
RP:
RD:
n:
m:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
2, 3
0, 1
PUD: PULL-UP DISABLE
PUD
PUD: PULL-UP DISABLE
WP:
WD:
RL:
RP:
RD:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD