Datasheet

146
ATmega323(L)
1457E–11/01
Figure 76. Port C Schematic Diagram (Pins PC2 - PC5). The JTAG interface on these
pins is not shown in the figure.
Figure 77. Port C Schematic Diagram (Pins PC6)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PCn
R
R
WP:
WD:
RL:
RP:
RD:
n:
WRITE PORTC
WRITE DDRC
READ PORTC LATCH
READ PORTC PIN
READ DDRC
2..5
DDCn
PORTCn
RL
RP
PUD
PUD: PULL-UP DISABLE
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PC6
R
R
WP:
WD:
RL:
RP:
RD:
AS2:
WRITE PORTC
WRITE DDRC
READ PORTC LATCH
READ PORTC PIN
READ DDRC
ASYNCH SELECT T/C2
DDC6
PORTC6
RL
RP
AS2
T/C2 OSC
AMP INPUT
PUD
0
1
PUD: PULL-UP DISABLE