Datasheet
121
ATmega323(L)
1457E–11/01
The Analog
Comparator
The analog comparator compares the input values on the positive pin PB2 (AIN0) and
negative pin PB3 (AIN1). When the voltage on the positive pin PB2 (AIN0) is higher than
the voltage on the negative pin PB3 (AIN1), the Analog Comparator Output, ACO, is set
(one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture
function. In addition, the comparator can trigger a separate interrupt, exclusive to the
Analog Comparator. The user can select Interrupt triggering on comparator output rise,
fall or toggle. A block diagram of the comparator and its surrounding logic is shown in
Figure 59
.
Figure 59. Analog Comparator Block Diagram
Note: See Figure 60 on page 125.
The Analog Comparator
Control and Status Register –
ACSR
• Bit 7 - ACD: Analog Comparator Disable
When this bit is set(one), the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator. This will reduce power con-
sumption in active and idle mode. When changing the ACD bit, the Analog Comparator
Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can
occur when the bit is changed.
• Bit 6 - ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap voltage of nominally 1.22 ± 0.10 V replaces the
positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the
positive input of the Analog Comparator. See “Internal Voltage Reference” on page 31.
• Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
ADEN
1)
Bit 76543210
$08 ($28)
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value00N/A00000