Datasheet

119
ATmega323(L)
1457E–11/01
ldi r16, 0x44 ; Load data(here, data=0x44)into TWDR register
out TWDR, r16
ldi r16, (1<<TWINT) | (1<<TWEA) | (1<<TWEN)
out TWCR, r16 ; Clear TWINT bit in TWCR to start transmission
; of data. Setting TWEA indicates that ACK
; should be received when transfer finished
wait16:in r16,TWCR ; Wait for TWINT flag set. This indicates that
sbrs r16, TWINT ; data has been transmitted, and ACK/NACK has
rjmp wait16 ; been received
in r16, TWSR ; Check value of TWI Status Register. If status
cpi r16, ST_DATA_ACK ; different from ST_DATA_ACK, go to ERROR
brne ERROR
ldi r16, 0x55 ; Load data(here, data=0x55)into TWDR register
out TWDR, r16
ldi r16, (1<<TWINT) | (1<<TWEN)
out TWCR, r16 ; Clear TWINT bit in TWCR to start transmission
; of data. Not setting TWEA indicates that
; NACK should be received after data byte
; Master signalling end of transmission)
wait17:in r16,TWCR ; Wait for TWINT flag set. This indicates that
sbrs r16, TWINT ; data has been transmitted, and ACK/NACK has
rjmp wait17 ; been received
in r16, TWSR ; Check value of TWI Status Register. If status
cpi r16, ST_LAST_DATA ; different from ST_LAST_DATA, go to ERROR
brne ERROR
ldi r16, (1<<TWINT) | (1<<TWEA) | (1<<TWEN)
out TWCR, r16 ; Continue address recognition in Slave
; Transmitter mode
TWI Include File ;***** General Master status codes *****
.equ START =$08 ;START has been transmitted
.equ REP_START =$10 ;Repeated START has been transmitted
;***** Master Transmitter status codes *****
.equ MT_SLA_ACK =$18 ;SLA+W has been transmitted and ACK received
.equ MT_SLA_NACK =$20 ;SLA+W has been transmitted and NACK received
.equ MT_DATA_ACK =$28 ;Data byte has been transmitted and ACK
;received
Table 41. Miscellaneous States
Status Code
(TWSR)
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
Next Action Taken by 2-wire Serial Interface Hardware
To/from TWDR
To TWCR
STA
STO TWINT TWEA
$F8 No relevant state information
available; TWINT = “0”
No TWDR action No TWCR action Wait or proceed current transfer
$00 Bus error due to an illegal
START or STOP condition
No TWDR action 0 1 1 X Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.