Datasheet
112
ATmega323(L)
1457E–11/01
Figure 56. Formats and States in the Master Receiver Mode
Assembly Code Example –
Master Receiver Mode
;Part specific include file and TWI include file must be included.
; <Initialize registers TWAR and TWBR>
ldi r16, (1<<TWINT) | (1<<TWSTA) | (1<<TWEN)
out TWCR, r16 ;Send START condition
wait5:in r16,TWCR ; Wait for TWINT flag set. This indicates that
sbrs r16, TWINT ; the START condition has been transmitted
rjmp wait5
in r16, TWSR ; Check value of TWI Status Register. If status
cpi r16, START ; different from START, go to ERROR
brne ERROR
ldi r16, 0xc9 ; Load SLA+R into TWDR register
out TWDR, r16
ldi r16, (1<<TWINT) | (1<<TWEN)
out TWCR, r16 ; Clear TWINT bit in TWCR to start transmission
; of SLA+R
wait6:in r16,TWCR ; Wait for TWINT flag set. This indicates that
sbrs r16, TWINT ; SLA+R has been transmitted, and ACK/NACK has
rjmp wait6 ; been received
S SLA R A DATA A
$08
$40 $50
S SLA R
$10
AP
$48
A or A
$38
Other master
continues
$38
Other master
continues
W
A
$68
Other master
continues
$78 $B0
To corresponding
states in slave mode
MR
MT
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
DATA A
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus
PDATA A
$58
A