Datasheet

106
ATmega323(L)
1457E–11/01
Assembly code illustrating operation of the master transmitter mode is given at the end
of the TWI section.
Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmit-
ter (see Figure 56). The transfer is initialized as in the master transmitter mode. When
the START condition has been transmitted, the TWINT flag is set by hardware. The soft-
ware must then load TWDR with the 7-bit slave address and the data direction bit
(SLA+R). The transfer will then continue when the TWINT flag is cleared by software.
When the slave address and the direction bit have been transmitted and an acknowl-
edgement bit has been received, TWINT is set again and a number of status codes in
TWSR are possible. Possible status codes in master mode are $40, $48, or $38. The
appropriate action to be taken for each of these status codes is detailed in Table .
Received data can be read from the TWDR register when the TWINT flag is set high by
hardware. This scheme is repeated until the last byte has been received and a STOP
condition is transmitted by writing a logic one to the TWSTO bit in the TWCR register.
After a repeated START condition (state $10), the 2-wire Serial Interface may switch to
the master transmitter mode by loading TWDR with SLA+W or access a new slave as
master receiver or transmitter.
Assembly code illustrating operation of the master receiver mode is given at the end of
the TWI section.
Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmit-
ter (see Figure 57). To initiate the slave receiver mode, TWAR and TWCR must be
initialized as follows:
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a master. If the LSB is set, the 2-wire Serial Interface will respond to the
general call address ($00), otherwise it will ignore the general call address.
TWEN must be set to enable the 2-wire Serial Interface. The TWEA bit must be set to
enable the acknowledgement of the device’s own slave address or the general call
address. TWSTA and TWSTO must be cleared.
When TWAR and TWCR have been initialized, the 2-wire Serial Interface waits until it is
addressed by its own slave address (or the general call address if enabled) followed by
the data direction bit which must be “0” (write) for the 2-wire Serial Interface to operate
in the slave receiver mode. After its own slave address and the write bit have been
received, the 2-wire Serial Interface interrupt flag is set and a valid status code can be
read from TWSR. The status code is used to determine the appropriate software action.
The appropriate action to be taken for each status code is detailed in Table 42. The
slave receiver mode may also be entered if arbitration is lost while the 2-wire Serial
Interface is in the master mode (see states $68 and $78).
If the TWEA bit is reset during a transfer, the 2-wire Serial Interface will return a “Not
Acknowledge” (“1”) to SDA after the next received data byte. While TWEA is reset, the
2-wire Serial Interface does not respond to its own slave address. However, the 2-wire
Serial Bus is still monitored and address recognition may resume at any time by setting
TWEA. This implies that the TWEA bit may be used to temporarily isolate the 2-wire
Serial Interface from the 2-wire Serial Bus.
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
Value Device’s Own Slave Address
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE
Value 0 100010 X