Datasheet
104
ATmega323(L)
1457E–11/01
The 2-wire Serial Interface
Data Register – TWDR
• Bits 7..0 - TWD: 2-wire Serial Interface Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the 2-wire Serial Bus.
In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the
TWDR contains the last byte received. It is writable while the 2-wire Serial Interface is
not in the process of shifting a byte. This occurs when the 2-wire Serial Interface inter-
rupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by
the user before the first interrupt occurs. The data in TWDR remain stable as long as
TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in.
TWDR always contains the last byte present on the bus, except after a wake up from
ADC Noise Reduction Mode, Power-down mode, or Power-save mode by the 2-wire
Serial Interface interrupt. For example, in the case of a lost bus arbitration, no data is
lost in the transition from Master to Slave. Handling of the ACK flag is controlled auto-
matically by the 2-wire Serial Interface logic, the CPU cannot access the ACK bit
directly.
The 2-wire Serial Interface
(Slave) Address Register –
TWAR
• Bits 7..1 - TWA: 2-wire Serial Interface (Slave) Address Register
These seven bits constitute the slave address of the 2-wire Serial Bus unit.
• Bit 0 - TWGCE: 2-wire Serial Interface General Call Recognition Enable bit
This bit enables, if set, the recognition of the General Call given over the 2-wire Serial
Bus.
The TWAR should be loaded with the 7-bit slave address (in the seven most significant
bits of TWAR) to which the 2-wire Serial Interface will respond when programmed as a
slave transmitter or receiver, and not needed in the master modes. The LSB of TWAR is
used to enable recognition of the general call address ($00). There is an associated
address comparator that looks for the slave address (or general call address if enabled)
in the received serial address. If a match is found, an interrupt request is generated.
2-wire Serial Interface
Modes
The 2-wire Serial Interface can operate in four different modes:
• Master Transmitter
• Master Receiver
• Slave Receiver
• Slave Transmitter
Data transfer in each mode of operation is shown in Figure 55 to Figure 58. These fig-
ures contain the following abbreviations:
S: START condition
R: Read bit (high level at SDA)
Bit 76543210
$03 ($23)
TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value11111111
Bit 76543210
$02 ($22)
TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value11111110