Datasheet
103
ATmega323(L)
1457E–11/01
2-wire Serial Interface waits until a STOP condition is detected, and then generates a
new START condition to claim the bus Master status.
• Bit 4 - TWSTO: 2-wire Serial Bus STOP Condition Flag
TWSTO is a stop condition flag. In Master mode setting the TWSTO bit in the control
register will generate a STOP condition on the 2-wire Serial Bus. When the STOP condi-
tion is executed on the bus, the TWSTO bit is cleared automatically. In slave mode
setting the TWSTO bit can be used to recover from an error condition. No stop condition
is generated on the bus then, but the 2-wire Serial Interface returns to a well-defined
unaddressed slave mode and releases the SCL and SDA lines to a high impedance
state.
• Bit 3 - TWWC: 2-wire Serial Bus Write Collision Flag
The TWWC bit is set when attempting to write to the 2-wire Serial Interface Data Regis-
ter
– TWDR when TWINT is low. This flag is cleared by writing the TWDR register when
TWINT is high.
• Bit 2 - TWEN: 2-wire Serial Interface Enable Bit
The TWEN bit enables 2-wire Serial Interface operation. If this bit is cleared (zero), the
bus outputs SDA and SCL are set to high impedance state, and the input signals are
ignored. The interface is activated by setting this bit (one).
• Bit 1 - Res: Reserved Bit
This bit is a reserved bit in the ATmega323 and will always read as zero.
• Bit 0 - TWIE: 2-wire Serial Interface Interrupt Enable
When this bit is enabled, and the I-bit in SREG is set, the 2-wire Serial Interface interrupt
will be activated for as long as the TWINT flag is high.
The TWCR is used to control the operation of the 2-wire Serial Interface. It is used to
enable the 2-wire Serial Interface, to initiate a master access by applying a START con-
dition to the bus, to generate a receiver acknowledge, to generate a stop condition, and
to control halting of the bus while the data to be written to the bus are written to the
TWDR. It also indicates a write collision if data is attempted written to TWDR while the
register is inaccessible.
The 2-wire Serial Interface
Status Register – TWSR
• Bits 7..3 - TWS: 2-wire Serial Interface Status
These 5 bits reflect the status of the 2-wire Serial Interface logic and the 2-wire Serial
Bus.
• Bits 2..0 - Res: Reserved bits
These bits are reserved in ATmega323 and will always read as zero
The TWSR is read only. It contains a status code which reflects the status of the 2-wire
Serial Interface logic and the 2-wire Serial Bus. There are 26 possible status codes.
When TWSR contains $F8, no relevant state information is available and no 2-wire
Serial Interface interrupt is requested. A valid status code is available in TWSR one
CPU clock cycle after the 2-wire Serial Interface interrupt flag (TWINT) is set by hard-
ware and is valid until one CPU clock cycle after TWINT is cleared by software. Table 37
to Table 44 give the status information for the various modes.
Bit 76543210
$01 ($21)
TWS7 TWS6 TWS5 TWS4 TWS3 - - - TWSR
Read/WriteRRRRRRRR
Initial Value11111000