Datasheet
102
ATmega323(L)
1457E–11/01
• Bits 7..0 - 2-wire Serial Interface Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a
frequency divider which generates the SCL clock frequency in the master modes
according to the following equation:
• Bit Rate = SCL frequency
• f
CK
= CPU Clock frequency
• TWBR = Contents of the 2-wire Serial Interface Bit Rate Register
• t
A
= Bus alignment adjustment
Note: Both the receiver and the transmitter can stretch the low period of the SCL line when
waiting for user response, thereby reducing the average bit rate.
TWBR should be set to a value higher than 7 to ensure correct 2-wire Serial Bus func-
tionality. The bus alignment adjustment is automatically inserted by the 2-wire Serial
Interface, and ensures the validity of setup and hold times on the bus for any TWBR
value higher than 7. This adjustment may vary from 200 ns to 600 ns depending on bus
loads and drive capabilities of the devices connected to the bus.
The 2-wire Serial Interface
Control Register – TWCR
• Bit 7 - TWINT: 2-wire Serial Interface Interrupt Flag
This bit is set by hardware when the 2-wire Serial Interface has finished its current job
and expects application software response. If the I-bit in the SREG and TWIE in the
TWCR register are set (one), the MCU will jump to the interrupt vector at address $026.
While the TWINT flag is set, the bus SCL clock line low period is stretched. The TWINT
flag must be cleared by software by writing a logic one to it. Note that this flag is not
automatically cleared by hardware when executing the interrupt routine. Also note that
clearing this flag starts the operation of the 2-wire Serial Interface, so all accesses to the
2-wire Serial Interface Address Register
– TWAR, 2-wire Serial Interface Status Register
– TWSR, and 2-wire Serial Interface Data Register – TWDR must be complete before
clearing this flag.
• Bit 6 - TWEA: 2-wire Serial Interface Enable Acknowledge Flag
TWEA flag controls the generation of the acknowledge pulse. If the TWEA bit is set, the
ACK pulse is generated on the 2-wire Serial Bus if the following conditions are met:
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in master receiver or slave receiver mode.
By setting the TWEA bit low, the device can be virtually disconnected from the 2-wire
Serial Bus temporarily. Address recognition can then be resumed by setting the TWEA
bit again.
• Bit 5 - TWSTA: 2-wire Serial Bus START Condition Flag
The TWSTA flag is set by the application when it desires to become a master on the 2-
wire Serial Bus. The 2-wire Serial Interface hardware checks if the bus is available, and
generates a START condition on the bus if it is free. However, if the bus is not free, the
Bit Rate
f
CK
16 2(TWBR) + t
A
f
CK
+
-----------------------------------------------------------=
Bit 76543210
$36 ($56)
TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE TWCR
Read/Write R/W R/W R/W R/W R R/W R R/W
Initial Value00000000