Datasheet
101
ATmega323(L)
1457E–11/01
Figure 54. Block diagram of the 2-wire Serial Interface
The CPU interfaces with the 2-wire Serial Interface via the following five I/O registers:
the 2-wire Serial Interface Bit Rate Register (TWBR), the 2-wire Serial Interface Control
Register (TWCR), the 2-wire Serial Interface Status Register (TWSR), the 2-wire Serial
Interface Data Register (TWDR), and the 2-wire Serial Interface Address Register
(TWAR, used in slave mode).
The 2-wire Serial Interface Bit
Rate Register – TWBR
ACK
INPUT
OUTPUT
INPUT
OUTPUT
START/STOP
AND SYNC
ARBITRATION
TIMING
AND
CONTROL
SERIAL CLOCK
GENERATOR
STATE MACHINE
AND
STATUS DECODER
DATA SHIFT
REGISTER
ADDRESS REGISTER
AND
COMPARATOR
TWAR
SDA
SCL
TWDR
CONTROL
REGISTER
STATUS
REGISTER
STATUS
TWCR
TWSR
AVR 8-BIT DATA BUS
Bit 76543210
$00 ($20)
TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000