Datasheet

80
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
EIFR – External Interrupt Flag
Register
• Bits 7:0 – INTF7:0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit,
INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured as
level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,
the input buffers on these pins will be disabled. This may cause a logic change in inter-
nal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes”
on page 87 for more information.
PCICR – Pin Change Interrupt
Control Register
• Bit 2 – PCIE2: Pin Change Interrupt Enable 1
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCI2 Interrupt Vector. PCINT23:16 pins are enabled individually by the
PCMSK2 Register.
• Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1
Register.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0
Register.
Bit 76543210
0x1C (0x3C) INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x68)
– – – – – PCIE2 PCIE1 PCIE0 PCICR
Read/WriteRRRRRR/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0