Datasheet

58
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Figure 24. Reset Logic
Notes: 1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling)
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-
tion level is defined in Table 26. The POR is activated whenever V
CC
is below the
detection level. The POR circuit can be used to trigger the start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-
ing the Power-on Reset threshold voltage invokes the delay counter, which determines
how long the device is kept in RESET after V
CC
rise. The RESET signal is activated
again, without any delay, when V
CC
decreases below the detection level.
Table 26. Reset Characteristics
(1)
Symbol Parameter Condition Min Typ Max Units
V
POT
Power-on Reset Threshold
Voltage (rising)
TBD TBD TBD V
Power-on Reset Threshold
Voltage (falling)
(2)
TBD TBD TBD V
V
RST
RESET Pin Threshold Voltage TBD TBD TBD V
t
RST
Minimum pulse width on RESET
Pin
TBD TBD TBD ns
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
JTRF
JTAG Reset
Register
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit