Datasheet

39
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as
shown below. The clock from the selected source is input to the AVR clock generator,
and routed to the appropriate modules.
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
Default Clock Source The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8
programmed, resulting in 1.0 MHz system clock. The startup time is set to maximum
and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default
setting ensures that all users can make their desired clock source setting using any
available programming interface.
Clock Start-up Sequence Any clock source needs a sufficient V
CC
to start oscillating and a minimum number of
oscillating cycles before it can be considered stable.
To ensure sufficient V
CC
, the device issues an internal reset with a time-out delay (t
TOUT
)
after the device reset is released by all other reset sources. “On-chip Debug System” on
page 53 describes the start conditions for the internal reset. The delay (t
TOUT
) is timed
from the Watchdog Oscillator and the number of cycles in the delay is set by the SUTx
and CKSELx fuse bits. The selectable delays are shown in Table 11. The frequency of
the Watchdog Oscillator is voltage dependent as shown in “Typical Characteristics” on
page 390.
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum
Vcc. The delay will not monitor the actual voltage and it will be required to select a delay
longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out
Detection circuit should be used. A BOD circuit will ensure sufficient Vcc before it
releases the reset, and the time-out delay can be disabled. Disabling the time-out delay
without utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is
considered stable. An internal ripple counter monitors the oscillator output clock, and
keeps the internal reset active for a given number of clock cycles. The reset is then
released and the device will start to execute. The recommended oscillator start-up time
Table 10. Device Clocking Options Select
(1)
Device Clocking Option CKSEL3:0
Low Power Crystal Oscillator 1111 - 1000
Full Swing Crystal Oscillator 0111 - 0110
Low Frequency Crystal Oscillator 0101 - 0100
Internal 128 kHz RC Oscillator 0011
Calibrated Internal RC Oscillator 0010
External Clock 0000
Reserved 0001
Table 11. Number of Watchdog Oscillator Cycles
Typ Time-out (V
CC
= 5.0V) Typ Time-out (V
CC
= 3.0V) Number of Cycles
0 ms 0 ms 0
4.1 ms 4.3 ms 512
65 ms 69 ms 8K (8,192)