Datasheet

388
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Figure 163. External Memory Timing (SRWn1 = 0, SRWn0 = 0
Figure 164. External Memory Timing (SRWn1 = 0, SRWn0 = 1)
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8
AddressPrev. addr.
DA7:0
Address
Data
Prev. data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4