Datasheet

376
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
4)The sum of all IOH, for ports E0-E7, G5 should not exceed 100 mA.
5)The sum of all IOH, for ports F0-F7, K0-K7 should not exceed 100 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrol-
lers manufactured in the same process technology. These values are preliminary values representing design targets, and
will be updated after characterization of actual silicon
6. Values with “PRR1 – Power Reduction Register 1” enabled (0xFF).
External Clock Drive
Waveforms
Figure 155. External Clock Drive Waveforms
External Clock Drive
Note: All DC Characteristics contained in this datasheet are based on simulation and charac-
terization of other AVR microcontrollers manufactured in the same process technology.
These values are preliminary values representing design targets, and will be updated
after characterization of actual silicon.
V
IL1
V
IH1
Table 167. External Clock Drive
Symbol Parameter
V
CC
=1.8-5.5V V
CC
=2.7-5.5V V
CC
=4.5-5.5V
UnitsMin. Max. Min. Max. Min. Max.
1/t
CLCL
Oscillator
Frequency
0208016MHz
t
CLCL
Clock Period 500 125 62.5 ns
t
CHCX
High Time 200 50 25 ns
t
CLCX
Low Time 200 50 25 ns
t
CLCH
Rise Time 2.0 1.6 0.5 μs
t
CHCL
Fall Time 2.0 1.6 0.5 μs
Δt
CLCL
Change in period
from one clock
cycle to the next
22 2%