Datasheet

356
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Notes: 1. t
WLRH
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock
bits commands.
2. t
WLRH_CE
is valid for the Chip Erase command.
Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using a serial pro-
gramming bus while RESET
is pulled to GND. The serial programming interface
consists of pins SCK, PDI (input) and PDO (output). After RESET
is set low, the Pro-
gramming Enable instruction needs to be executed first before program/erase
operations can be executed. NOTE, in Table 163 on page 356, the pin mapping for
serial programming is listed. Not all packages use the SPI pins dedicated for the internal
Serial Peripheral Interface - SPI.
Serial Programming Pin
Mapping
Figure 147. Serial Programming and Verify
(1)
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock
source to the XTAL1 pin.
2. V
CC
- 0.3V < AVCC < V
CC
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
t
BVDV
BS1 Valid to DATA valid 0 250 ns
t
OLDV
OE Low to DATA Valid 250 ns
t
OHDZ
OE High to DATA Tri-stated 250 ns
Table 162. Parallel Programming Characteristics, V
CC
= 5V ± 10% (Continued)
Symbol Parameter Min Typ Max Units
Table 163. Pin Mapping Serial Programming
Symbol
Pins
(TQFP-100)
Pins
(TQFP-64) I/O Description
PDI PB2 PE0 I Serial Data in
PDO PB3 PE1 O Serial Data out
SCK PB1 PB1 I Serial Clock
VCC
GND
XTAL1
SCK
PDO
PDI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)