Datasheet

295
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ADCSRB – ADC Control and
Status Register B
• Bit 3 – MUX5: Analog Channel and Gain Selection Bit
This bit is used together with MUX4:0 in ADMUX to select which combination in of ana-
log inputs are connected to the ADC. See Table 129 for details. If this bit is changed
during a conversion, the change will not go in effect until this conversion is complete.
This bit is not valid for ATmega1281/2561.
Bit 76543210
(0x7B)
– ACME – –MUX5ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W RRR/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 129. Input Channel Selections
MUX5:0
Single Ended
Input
Positive Differential
Input
Negative Differential
Input Gain
000000 ADC0
N/A
000001 ADC1
000010 ADC2
000011 ADC3
000100 ADC4
000101 ADC5
000110 ADC6
000111 ADC7
001000
(1)
N/A
ADC0 ADC0 10x
001001
(1)
ADC1 ADC0 10x
001010
(1)
ADC0 ADC0 200x
001011
(1)
ADC1 ADC0 200x
001100
(1)
ADC2 ADC2 10x
001101
(1)
ADC3 ADC2 10x
001110
(1)
ADC2 ADC2 200x
001111
(1)
ADC3 ADC2 200x
010000 ADC0 ADC1 1x
010001 ADC1 ADC1 1x
010010 ADC2 ADC1 1x
010011 ADC3 ADC1 1x
010100 ADC4 ADC1 1x
010101 ADC5 ADC1 1x
010110 ADC6 ADC1 1x
010111 ADC7 ADC1 1x
011000 ADC0 ADC2 1x
011001 ADC1 ADC2 1x