Datasheet

285
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Differential Channels When using differential channels, certain aspects of the conversion need to be taken
into consideration.
Differential conversions are synchronized to the internal clock CK
ADC2
equal to half the
ADC clock. This synchronization is done automatically by the ADC interface in such a
way that the sample-and-hold occurs at a specific phase of CK
ADC2
. A conversion initi-
ated by the user (i.e., all single conversions, and the first free running conversion) when
CK
ADC2
is low will take the same amount of time as a single ended conversion (13 ADC
clock cycles from the next prescaled clock cycle). A conversion initiated by the user
when CK
ADC2
is high will take 14 ADC clock cycles due to the synchronization mecha-
nism. In Free Running mode, a new conversion is initiated immediately after the
previous conversion completes, and since CK
ADC2
is high at this time, all automatically
started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the
ADC must be switched off between conversions. When Auto Triggering is used, the
ADC prescaler is reset before the conversion is started. Since the stage is dependent of
a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling
and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to
“0” then to “1”), only extended conversions are performed. The result from the extended
conversions will be valid. See “Prescaling and Conversion Timing” on page 282 for tim-
ing details.
Table 126. ADC Conversion Time
Condition
Sample & Hold (Cycles
from Start of Conversion)
Conversion Time
(Cycles)
First conversion 13.5 25
Normal conversions, single ended 1.5 13
Auto Triggered conversions 2 13.5
Normal conversions, differential 1.5/2.5 13/14