Datasheet

280
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Figure 113. Analog to Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
8-BIT DATABUS
15 0
ADIE
ADFR
ADSC
ADEN
ADIF
ADIF
MUX[4:0]
ADPS[2:0]
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
(1.1V/2.56V)
AVCC
REFS[1:0]
ADLAR
CHANNEL SELECTION
ADC[9:0]
ADC
MULTIPLEXER
OUTPUT
GAIN
AMPLIFIE
R
AREF
BANDGAP (1.1V)
REFERENCE
GND
CONVERSION LOGIC
ADC CTRL & STATUS
REGISTER B (ADCSRB)
ADC CTRL & STATUS
REGISTER A (ADCSRA)
PRESCALER
ADC MULTIPLEXER
SELECT (ADMUX)
MUX DECODER
DIFF / GAIN SELECT
ADC DATA REGISTER
(ADCH/ADCL)
ADC[2:0]
TRIGGER
SELECT
START
INTERRUPT
FLAGS
ADTS[2:0]
+
-
ADC[15:0]
+
-
10-bit DAC
MUX[5]
ADC[10:8]