Datasheet

231
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous
mode is used. The UCPOLn bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCKn).
UBRRnL and UBRRnH –
USART Baud Rate Registers
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit
must be written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the
four most significant bits, and the UBRRL contains the eight least significant bits of the
USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor-
rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of
the baud rate prescaler.
Table 108. UCPOLn Bit Settings
UCPOLn
Transmitted Data Changed (Output
of TxDn Pin)
Received Data Sampled (Input on
RxDn Pin)
0 Rising XCKn Edge Falling XCKn Edge
1 Falling XCKn Edge Rising XCKn Edge
Bit 151413121110 9 8
–––– UBRR[11:8] UBRRHn
UBRR[7:0] UBRRLn
76543210
Read/WriteRRRRR/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000