Datasheet

212
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Internal Clock Generation –
The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master
modes of operation. The description in this section refers to Figure 83.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it func-
tion as a programmable prescaler or baud rate generator. The down-counter, running at
system clock (f
osc
), is loaded with the UBRRn value each time the counter has counted
down to zero or when the UBRRLn Register is written. A clock is generated each time
the counter reaches zero. This clock is the baud rate generator clock output (=
f
osc
/(UBRRn+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or
16 depending on mode. The baud rate generator output is used directly by the
Receiver’s clock and data recovery units. However, the recovery units use a state
machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn,
U2Xn and DDR_XCKn bits.
Table 101 contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRRn value for each mode of operation using an internally generated
clock source.
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRRnContents of the UBRRHn and UBRRLn Registers, (0-4095)
Table 101. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating
Baud Rate
(1)
Equation for Calculating
UBRR Value
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn =
1)
Synchronous Master
mode
BAUD
f
OSC
16 UBRRn 1+()
------------------------------------------=
UBRRn
f
OSC
16BAUD
------------------------ 1–=
BAUD
f
OSC
8 UBRRn 1+()
---------------------------------------=
UBRRn
f
OSC
8BAUD
-------------------- 1–=
BAUD
f
OSC
2 UBRRn 1+()
---------------------------------------=
UBRRn
f
OSC
2BAUD
-------------------- 1–=