Datasheet

204
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
SS Pin Functionality
Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When
SS
is held low, the SPI is activated, and MISO becomes an output if configured so by
the user. All other pins are inputs. When SS
is driven high, all pins are inputs, and the
SPI is passive, which means that it will not receive incoming data. Note that the SPI
logic will be reset once the SS
pin is driven high.
The SS
pin is useful for packet/byte synchronization to keep the slave bit counter syn-
chronous with the master clock generator. When the SS
pin is driven high, the SPI slave
will immediately reset the send and receive logic, and drop any partially received data in
the Shift Register.
Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine
the direction of the SS
pin.
If SS
is configured as an output, the pin is a general output pin which does not affect the
SPI system. Typically, the pin will be driving the SS
pin of the SPI Slave.
If SS
is configured as an input, it must be held high to ensure Master SPI operation. If
the SS
pin is driven low by peripheral circuitry when the SPI is configured as a Master
with the SS
pin defined as an input, the SPI system interprets this as another master
selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the
SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a
result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in
SREG is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a
possibility that SS
is driven low, the interrupt should always check that the MSTR bit is
still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to
re-enable SPI Master mode.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 80 and Figure 81. Data bits are shifted out and latched in on oppo-
site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing Table 98 and Table 99, as done below: