Datasheet

199

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

SPI – Serial Peripheral Interface

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the ATmega640/1280/1281/2560/2561 and peripheral devices or between sev-

eral AVR devices. The ATmega640/1280/1281/2560/2561 SPI includes the following

features:

•

Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 236.

The Power Reduction SPI bit, PRSPI, in “PRR0 – Power Reduction Register 0” on page

55 on page 50 must be written to zero to enable SPI module.

Figure 78. SPI Block Diagram

(1)

Note: 1. Refer to Figure 1 on page 2, and Table 42 on page 92 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 79.

The system consists of two shift Registers, and a Master clock generator. The SPI Mas-

ter initiates the communication cycle when pulling low the Slave Select SS

pin of the

desired Slave. Master and Slave prepare the data to be sent in their respective shift

SPI2X

DIVIDER

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