Datasheet

198

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

• Bit 0 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A

(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the

Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter2 changes counting direction at 0x00.

GTCCR – General

Timer/Counter Control

• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2

W hen this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally

cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating

in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit

will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7

– TSM: Timer/Counter Synchronization Mode” on page 173 for a description of the

Timer/Counter Synchronization mode.

Bit 7 6 5 4 3 2 1 0

0x23 (0x43)

TSM – – – – –PSRASYPSRSYNC GTCCR

Read/Write R/W RR RRRR/W R/W

Initial Value 0 0 0 0 0 0 0 0