Datasheet

191
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Register Description
TCCR2A –Timer/Counter
Control Register A
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the
COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-
responding to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 88 shows the COM2A1:0 bit functionality when the
WGM22:0 bits are set to a normal or CTC mode (non-PWM).
Table 89 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast
PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast
PWM Mode” on page 180 for more details.
Table 90 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to
phase correct PWM mode.
Bit 7 6 5 4 3 2 1 0
(0xB0)
COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 TCCR2A
Read/Write R/W R/W R/W R/W RRR/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 88. Compare Output Mode, non-PWM Mode
COM2A1 COM2A0 Description
00Normal port operation, OC2A disconnected.
0 1 Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match
1 1 Set OC2A on Compare Match
Table 89. Compare Output Mode, Fast PWM Mode
(1)
COM2A1 COM2A0 Description
00Normal port operation, OC2A disconnected.
01WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1 0 Clear OC2A on Compare Match, set OC2A at BOTTOM,
(non-inverting mode).
1 1 Set OC2A on Compare Match, clear OC2A at BOTTOM,
(inverting mode).