Datasheet

185
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when
the Timer/Counter clock is enabled.
Using the Output Compare
Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT2 when using the Output
Compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT2 equals the OCR2x value, the compare match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC2x should be performed before setting the Data Direction Register
for the port pin to output. The easiest way of setting the OC2x value is to use the Force
Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its
value even when changing between Waveform Generation modes.
Be aware that the COM2x1:0 bits are not double buffered together with the compare
value. Changing the COM2x1:0 bits will take effect immediately.
Compare Match Output
Unit
The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Gener-
ator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next
compare match. Also, the COM2x1:0 bits control the OC2x pin output source. Figure 72
shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O
Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0
bits are shown. When referring to the OC2x state, the reference is for the internal OC2x
Register, not the OC2x pin.
Figure 72. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC2x) from the
Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BUS
FOCnx
clk
I/O