Datasheet

169
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
TIMSK1 – Timer/Counter 1
Interrupt Mask Register
TIMSK3 – Timer/Counter 3
Interrupt Mask Register
TIMSK4 – Timer/Counter 4
Interrupt Mask Register
TIMSK5 – Timer/Counter 5
Interrupt Mask Register
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
OCFnC Flag, located in TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
OCFnB Flag, located in TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
OCFnA Flag, located in TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 69.) is executed when the TOVn Flag, located
in TIFRn, is set.
Bit 76543210
(0x6F)
– –ICIE1– OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x71)
– –ICIE3– OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x72)
– –ICIE4– OCIE4C OCIE4B OCIE4A TOIE4 TIMSK4
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x73)
– –ICIE5– OCIE5C OCIE5B OCIE5A TOIE5 TIMSK5
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0