Datasheet

149
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
A change of the COMnx1:0 bits state will have effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOCnx strobe bits.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and
Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the out-
put should be set, cleared or toggle at a compare match (See “Compare Match Output
Unit” on page 148.)
Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 157.
Table 82. Waveform Generation Mode Bit Description
(1)
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter
Mode of Operation TOP
Update of
OCRnx at
TOVn Flag
Set on
00 0 0 0Normal 0xFFFF Immediate MAX
10 0 0 1PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
20 0 1 0PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
30 0 1 1PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
50 1 0 1Fast PWM, 8-bit 0x00FF BOTTOM TOP
60 1 1 0Fast PWM, 9-bit 0x01FF BOTTOM TOP
70 1 1 1Fast PWM, 10-bit 0x03FF BOTTOM TOP
81 0 0 0PWM, Phase and Frequency
Correct
ICRn BOTTOM BOTTOM
91 0 0 1PWM,Phase and Frequency
Correct
OCRnA BOTTOM BOTTOM
101010PWM, Phase Correct ICRn TOP BOTTOM
111011PWM, Phase Correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
13 1 1 0 1 (Reserved) – – –
141110Fast PWM ICRn BOTTOM TOP
151111Fast PWM OCRnA BOTTOM TOP