Datasheet

132
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Table 75 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to
phase correct PWM mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-
rect PWM Mode” on page 126 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used, see Table 79. Modes of operation sup-
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare
Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see
“Modes of Operation” on page 149).
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
Table 78. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0B1 COM0B0 Description
00Normal port operation, OC0B disconnected.
01Reserved
1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Table 79. Waveform Generation Mode Bit Description
Mode WGM2 WGM1 WGM0
Timer/Counter
Mode of
Operation TOP
Update of
OCRx at
TOV Flag
Set on
(1)(2)
00 0 0Normal 0xFF Immediate MAX
10 0 1PWM, Phase
Correct
0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
41 0 0Reserved – – –
51 0 1PWM, Phase
Correct
OCRA TOP BOTTOM
61 1 0Reserved – – –
7 1 1 1 Fast PWM OCRA BOTTOM TOP