Datasheet

129
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
Figure 47 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 47. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with
Prescaler (f
clk_I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)