Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – 64K/128K/256K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-Sy
Pin Configurations 2 80 PA1 (AD1) 81 PA2 (AD2) 82 PJ7 83 PA0 (AD0) 84 GND 85 VCC 86 PK7 (ADC15/PCINT23) 87 PK5 (ADC13/PCINT21) 88 PK6 (ADC14/PCINT22) 89 PK3 (ADC11/PCINT19) 90 PK4 (ADC12/PCINT20) 91 PK1 (ADC9/PCINT17) PK0 (ADC8/PCINT16) 92 PK2 (ADC10/PCINT18) PF7 (ADC7/TDI) 93 PF5 (ADC5/TMS) 94 PF6 (ADC6/TDO) 95 PF3 (ADC3) 96 PF4 (ADC4/TCK) 97 PF1 (ADC1) 98 PF2 (ADC2) AREF 100 99 PF0 (ADC0) GND AVCC Figure 1.
ATmega640/1280/1281/2560/2561 Figure 2. CBGA-pinout ATmega640/1280/2560 Top view 1 2 3 4 5 6 Bottom view 7 8 9 10 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K Table 1. CBGA-pinout ATmega640/1280/2560.
PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 54 53 52 51 50 49 PF5 (ADC5/TMS) 57 PF6 (ADC6/TDO) PF4 (ADC4/TCK) 58 55 PF3 (ADC3) 59 56 PF1 (ADC1) PF2 (ADC2) 60 AREF PF0 (ADC0) 62 63 61 AVCC GND (OC0B) PG5 1 48 PA3 (AD3) (RXD0/PCINT8/PDI) PE0 2 47 PA4 (AD4) (TXD0/PDO) PE1 3 46 PA5 (AD5) (XCK0/AIN0) PE2 4 45 PA6 (AD6) (OC3A/AIN1) PE3 5 44 PA7 (AD7) (OC3B/INT4) PE4 6 43 PG2 (ALE) (OC3C/INT5) PE5 7 42 PC7 (A15) (T3/INT6) PE6 8 41 PC6 (A14)
ATmega640/1280/1281/2560/2561 Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 4. Block Diagram PF7..0 PK7..0 PORT F (8) PORT K (8) PJ7..0 PE7..
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega640/1280/1281/2560/2561 Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2 summarizes the different configurations for the six devices. Table 2.
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 97. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability.
ATmega640/1280/1281/2560/2561 Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running.
AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 5.
ATmega640/1280/1281/2560/2561 the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
ATmega640/1280/1281/2560/2561 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7. Figure 7.
ATmega640/1280/1281/2560/2561 RAMPZ – Extended Z-pointer Register for ELPM/SPM Bit 7 6 5 4 3 2 1 0 0x3B (0x5B) RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 8. Note that LPM is not affected by the RAMPZ setting. Figure 8.
Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 10 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
ATmega640/1280/1281/2560/2561 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
neously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
ATmega640/1280/1281/2560/2561 AVR Memories This section describes the different memories in the ATmega640/1280/1281/2560/2561. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega640/1280/1281/2560/2561 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
SRAM Data Memory Table 4 on page 21 shows how the ATmega640/1280/1281/2560/2561 SRAM Memory is organized. The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega640/1280/1281/2560/2561 all these addressing modes. The Register File is described in “General Purpose Register File” on page 13. Table 4. Data Memory Map Address (HEX) 0 - 1F 32 Registers 20 - 5F 64 I/O Registers 60 - 1FF 416 External I/O Registers 200 Internal SRAM (8192 x 8) 21FF 2200 External SRAM (0 - 64K x 8) FFFF Data Memory Access Times This section describes the general access timing concepts for internal memory access.
EEPROM Data Memory The ATmega640/1280/1281/2560/2561 contains 4K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
ATmega640/1280/1281/2560/2561 Assembly Code Example() EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega640/1280/1281/2560/2561 I/O Memory The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in “Register Summary” on page 416. All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
External Memory Interface With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The main features are: • Four different wait-state settings (including no wait-state).
ATmega640/1280/1281/2560/2561 For details about the port override, see the alternate functions in section “I/O-Ports” on page 83. The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, data, and the control signals on the ports according to Figure 15 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer.
Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be disabled and enabled in software as described in “XMCRB – External Memory Control Register B” on page 36.
ATmega640/1280/1281/2560/2561 Figure 16. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data Address Data Write XX WR Address Read Data Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
Figure 18. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data XX Write Address Data WR Read Address Data Data RD Note: Using all Locations of External Memory Smaller than 64 KB 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega640/1280/1281/2560/2561 Using all 64KB Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 13, only 56KB of External Memory is available by default (address space 0x0000 to 0x21FF is reserved for internal memory). However, it is possible to take advantage of the entire External Memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address.
Register Description EEPROM registers EEARH and EEARL – The EEPROM Address Register Bit 15 14 13 12 11 10 9 8 0x22 (0x42) – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 Read/Write Initial Value R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 X X X X X X X X X X X X • Bits 15:12 – Res: Reserved Bits These bits are reserved bits and will always read
ATmega640/1280/1281/2560/2561 Table 6. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Operation Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.
• Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation.
ATmega640/1280/1281/2560/2561 address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits. Table 7.
XMCRB – External Memory Control Register B Bit 7 6 5 4 3 2 1 0 XMBK – – – – XMM2 XMM1 XMM0 Read/Write R/W R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x75) XMCRB • Bit 7– XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the bus keeper.
ATmega640/1280/1281/2560/2561 System Clock and Clock Options This section describes the clock options for the AVR microcontroller. Overview Figure 20 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 50. The clock systems are detailed below. Figure 20.
Clock Systems and their Distribution CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
ATmega640/1280/1281/2560/2561 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 10.
is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal. The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Powerdown mode, Vcc is assumed to be at a sufficient level and only the start-up time is included.
ATmega640/1280/1281/2560/2561 4. Max frequency when using ceramic oscillator is 10 MHz. The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in Table 13. Table 13. Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1:0 Ceramic resonator, fast rising power 258 CK 14CK + 4.
Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 21. Either a quartz crystal or a ceramic resonator may be used. This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving other clock inputs and in noisy environments. The current consumption is higher than the “Low Power Crystal Oscillator” on page 40.
ATmega640/1280/1281/2560/2561 Table 15. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Oscillator Source / Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1:0 (1) 0 00 Ceramic resonator, fast rising power 258 CK 14CK + 4.1 ms Ceramic resonator, slowly rising power 258 CK 14CK + 65 ms(1) 0 01 Ceramic resonator, BOD enabled 1K CK 14CK(2) 0 10 Ceramic resonator, fast rising power 1K CK 14CK + 4.
Low Frequency Crystal Oscillator The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Frequency Crystal Oscillator. The crystal should be connected as shown in Figure 21. When this Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in Table 16. Table 16. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.
ATmega640/1280/1281/2560/2561 Table 18. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1:0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms(1) 10 Power Conditions Reserved Note: 128 kHz Internal Oscillator 11 1. The device is shipped with this option selected.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 23. Table 21. Crystal Oscillator Clock Frequency Nominal Frequency CKSEL3:0 0 - 16 MHz 0000 Table 22. Start-up Times for the External Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1:0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.
ATmega640/1280/1281/2560/2561 System Clock Prescaler The ATmega640/1280/1281/2560/2561 has a system clock prescaler, and the system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 48. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.
Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
ATmega640/1280/1281/2560/2561 device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 23.
Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. Sleep Modes Figure 20 on page 37 presents the different clock systems in the ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
ATmega640/1280/1281/2560/2561 Idle Mode When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Powersave mode. If the Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If the Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2.
ATmega640/1280/1281/2560/2561 Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 60 for details on how to configure the Brown-out Detector.
Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 25. Table 25.
ATmega640/1280/1281/2560/2561 PRR0 – Power Reduction Register 0 Bit 7 6 5 4 3 2 1 0 PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x64) PRR0 • Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.
PRR1 – Power Reduction Register 1 Bit 7 6 5 4 3 2 1 0 (0x65) – – PRTIM5 PRTIM4 PRTIM3 PRUSART3 PRUSART2 PRUSART1 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR1 • Bit 7:6 - Res: Reserved bits These bits are reserved and will always read as zero. • Bit 5 - PRTIM5: Power Reduction Timer/Counter5 Writing a logic one to this bit shuts down the Timer/Counter5 module.
ATmega640/1280/1281/2560/2561 System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 24. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 26.
ATmega640/1280/1281/2560/2561 Figure 25. MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 26. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 26) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Brown-out Detection ATmega640/1280/1281/2560/2561 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 27.
ATmega640/1280/1281/2560/2561 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See “Watchdog Timer” on page 53. for details on operation of the Watchdog Timer. Figure 29. Watchdog Reset During Operation CC CK Internal Voltage Reference ATmega640/1280/1281/2560/2561 features an internal bandgap reference.
Watchdog Timer ATmega640/1280/1281/2560/2561 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 128kHz OSCILLATOR OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K Figure 30.
ATmega640/1280/1281/2560/2561 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watchdog Timer.
Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
ATmega640/1280/1281/2560/2561 The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<
Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
ATmega640/1280/1281/2560/2561 Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt.
. Table 31. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
ATmega640/1280/1281/2560/2561 Interrupts This section describes the specifics of the interrupt handling as performed in ATmega640/1280/1281/2560/2561. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 17. Interrupt Vectors in ATmega640/1280/1281/2560/2561 Table 32. Reset and Interrupt Vectors Vector No.
Table 32. Reset and Interrupt Vectors (Continued) Vector No.
ATmega640/1280/1281/2560/2561 Reset and Interrupt Vector placement Table 33 on page 71 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 33.
0x0040 jmp TIM3_COMPA ; Timer3 CompareA Handler 0x0042 jmp TIM3_COMPB ; Timer3 CompareB Handler 0x0044 jmp TIM3_COMPC ; Timer3 CompareC Handler 0x0046 jmp TIM3_OVF ; Timer3 Overflow Handler 0x0048 jmp USART1_RXC ; USART1 RX Complete Handler 0x004A jmp USART1_UDRE ; USART1,UDR Empty Handler 0x004C jmp USART1_TXC ; USART1 TX Complete Handler 0x004E jmp TWI ; 2-wire Serial Handler 0x0050 jmp SPM_RDY ; SPM Ready Handler 0x0052 jmp TIM4_CAPT ; Timer4 Capture Handler 0x0054
ATmega640/1280/1281/2560/2561 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments 0x00000 RESET: ldi 0x00001 out SPH,r16 0x00002 ldi r16,low(RAMEND) 0x00003 0x00004 out sei SPL,r16 0x00005 r16,high(RAMEND) ; Main program start ; Set Stack Pointer to top of RAM
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments ; .org 0x1F000 0x1F000 0x1F002 jmp jmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler 0x1F004 jmp EXT_INT1 ; IRQ1 Handler ... ... ...
ATmega640/1280/1281/2560/2561 75 2549K–AVR–01/07
Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
ATmega640/1280/1281/2560/2561 External Interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
ATmega640/1280/1281/2560/2561 EICRB – External Interrupt Control Register B Bit 7 6 5 4 3 2 1 0 ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x6A) EICRB • Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set.
EIFR – External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x1C (0x3C) EIFR • Bits 7:0 – INTF7:0: External Interrupt Flags 7 - 0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one).
ATmega640/1280/1281/2560/2561 PCIFR – Pin Change Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x1B (0x3B) – – – – – PCIF2 PCIF1 PCIF0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCIFR • Bit 2 – PCIF2: Pin Change Interrupt Flag 1 When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
ATmega640/1280/1281/2560/2561 I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 33 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 33.
ATmega640/1280/1281/2560/2561 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
Figure 34. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega640/1280/1281/2560/2561 resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega640/1280/1281/2560/2561 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 36 shows how the port pin control signals from the simplified Figure 33 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 36.
Table 38 summarizes the function of the overriding signals. The pin and port indexes from Figure 36 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 38. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 39.
Table 41.
ATmega640/1280/1281/2560/2561 PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source. • OC1B/PCINT6, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source.
When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source. • SS/PCINT0 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low.
ATmega640/1280/1281/2560/2561 Table 44.
Table 46. Overriding Signals for Alternate Functions in PC7:PC4 Signal Name PC7/A15 PC6/A14 PC5/A13 PC4/A12 PUOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) PUOV 0 0 0 0 DDOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) DDOV 1 1 1 1 PVOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) PVOV A15 A14 A13 A12 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Table 47.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 48. Table 48.
• INT1/SDA – Port D, Bit 1 INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU. SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.
ATmega640/1280/1281/2560/2561 Table 50.
CLKO - Divided System Clock: The divided system clock can be output on the PE7 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTE7 and DDE7 settings. It will also be output during reset. • INT6/T3 – Port E, Bit 6 INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. T3, Timer/Counter3 counter source. • INT5/OC3C – Port E, Bit 5 INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source.
ATmega640/1280/1281/2560/2561 • PDI/RXD0/PCINT8 – Port E, Bit 0 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega1281/2561. For ATmega640/1280/2560 this function is placed on MOSI. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0.
Table 53. Overriding Signals for Alternate Functions in PE3:PE0 PE2/AIN0/XCK0 PE1/PDO(1)/ TXD0 PE0/PDI(1)/ RXD0/PCINT8 0 0 TXEN0 RXEN0 PUOV 0 0 0 PORTE0 • PUD DDOE 0 XCK0 OUTPUT ENABLE TXEN0 RXEN0 DDOV 0 1 1 0 PVOE OC3B ENABLE XCK0 OUTPUT ENABLE TXEN0 0 PVOV OC3B XCK0 OUTPUT TXD0 0 DIEOE 0 0 0 PCINT8 • PCIE1 DIEOV 0 0 0 1 DI 0 XCK0 INPUT – RXD0 PE0 0 0 0 PCINT8 INPUT AIO AIN1 INPUT AIN0 INPUT – – Signal Name PE3/AIN1/OC3A PUOE Note: 102 1.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 54. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. Table 54.
• ADC3 – ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3:0. Table 55.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port G The Port G alternate pin configuration is as follows: Table 57.
Table 58. Overriding Signals for Alternate Functions in PG5:PG4 Signal Name — — PG5/OC0B PG4/TOSC1 PUOE – – – AS2 PUOV – – – 0 DDOE – – – AS2 DDOV – – – 0 PVOE – – OC0B Enable 0 PVOV – – OC0B 0 PTOE – – – – DIEOE – – – AS2 DIEOV – – – EXCLK DI – – – – AIO – – – T/C2 OSC INPUT Table 59.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port H The Port H alternate pin configuration is as follows: Table 60.
• RXD2 – Port H, Bit 0 RXD2, USART2 Receive pin: Receive Data (Data input pin for the USART2). When the USART2 Receiver is enabled, this pin is configured as an input regardless of the value of DDH0. When the USART2 forces this pin to be an input, a logical on in PORTH0 will turn on the internal pull-up. Table 61.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port J The Port J alternate pin configuration is as follows: Table 63.
Table 64. Overriding Signals for Alternate Functions in PJ7:PJ4 Signal Name PJ7 PJ6/ PCINT15 PJ5/ PCINT14 PJ4/ PCINT13 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE - - - - DIEOE 0 PCINT15·PCIE1 PCINT14·PCIE1 PCINT13·PCIE1 DIEOV 0 1 1 1 DI 0 PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT AIO - - - - Table 65.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port K The Port K alternate pin configuration is as follows: Table 66.
Table 68.
ATmega640/1280/1281/2560/2561 Alternate Functions of Port L The Port L alternate pin configuration is as follows: Table 69.
Table 70 and Table 71 relates the alternate functions of Port L to the overriding signals shown in Figure 36 on page 89. Table 70. Overriding Signals for Alternate Functions in PL7:PL4 Signal Name PL7 PL6 PL5/OC5C PL4/OC5B PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE – – 0 0 DDOV – – 0 0 PVOE – – OC5C ENABLE OC5B ENABLE PVOV – – OC5C OC5B PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI 0 0 0 0 AIO – – – – Table 71.
ATmega640/1280/1281/2560/2561 Register Description for I/O-Ports MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the I/O ports pull-up resistors are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn, PORTxn} = 0b01).
PORTC – Port C Data Register Bit DDRC – Port C Data Direction Register PINC– Port C Input Pins Address 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x07 (0x27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x06
ATmega640/1280/1281/2560/2561 PORTF – Port F Data Register Bit DDRF – Port F Data Direction Register PINF – Port F Input Pins Address 7 6 5 4 3 2 1 0 0x11 (0x31) PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x10 (0x30) DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bi
PORTJ – Port J Data Register Bit 7 6 5 4 3 2 1 0 PORTJ7 PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x105) DDRJ – Port J Data Direction Register Bit 7 6 5 4 3 2 1 0 DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x104) PINJ – Port J Input Pins Address Bit 7 6 5 4 3 2 1 0 PINJ5 PINJ
ATmega640/1280/1281/2560/2561 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation.
Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 121. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B.
ATmega640/1280/1281/2560/2561 Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega640/1280/1281/2560/2561 Compare Match Output Unit The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 40 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega640/1280/1281/2560/2561 Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
ATmega640/1280/1281/2560/2561 Figure 43. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • Timer/Counter Timing Diagrams The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures.
ATmega640/1280/1281/2560/2561 Figure 47 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 47.
Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
ATmega640/1280/1281/2560/2561 Table 75. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: Description 1.
Table 75 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 78. Compare Output Mode, Phase Correct PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
ATmega640/1280/1281/2560/2561 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
Table 80. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
ATmega640/1280/1281/2560/2561 TIMSK0 – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bits 7:3, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting.
ATmega640/1280/1281/2560/2561 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • • • • • • • • • • • Overview True 16-bit Design (i.e.
Figure 48. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic TCLK Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform Generation = OCnA OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation DATABUS = OCnB OCRnB OCFnC (Int.Req.) Waveform Generation = OCnC OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.
ATmega640/1280/1281/2560/2561 also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See “AC – Analog Comparator” on page 275.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. See “About Code Examples” on page 9. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
ATmega640/1280/1281/2560/2561 The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega640/1280/1281/2560/2561 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see “Timer/Counter 0, 1, 3, 4, and 5 Prescaler” on page 172.
how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 149. The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
ATmega640/1280/1281/2560/2561 Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value.
(ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle.
ATmega640/1280/1281/2560/2561 The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register).
Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 52 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega640/1280/1281/2560/2561 A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits.
Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero.
ATmega640/1280/1281/2560/2561 OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1).
Figure 54. Fast PWM Mode, Timing Diagram OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value.
ATmega640/1280/1281/2560/2561 and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ---------------------------------N ⋅ ( 1 + TOP ) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode.
Figure 55. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
ATmega640/1280/1281/2560/2561 frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 ⋅ N ⋅ TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 56. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
ATmega640/1280/1281/2560/2561 The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 59. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 60 shows the same timing data, but with the prescaler enabled.
ATmega640/1280/1281/2560/2561 Figure 60.
Register Description TCCR1A – Timer/Counter 1 Control Register A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x80) TCCR3A – Timer/Counter 3 Control Register A Bit 7 6 5 4 3 2 1 0 COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x90) TCCR4A – Timer/Counte
ATmega640/1280/1281/2560/2561 . Table 83. Compare Output Mode, non-PWM COMnA1 COMnB1 COMnC1 COMnA0 COMnB0 COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 Toggle OCnA/OCnB/OCnC on compare match. 1 0 Clear OCnA/OCnB/OCnC on compare match (set output to low level). 1 1 Set OCnA/OCnB/OCnC on compare match (set output to high level). Description Table 84 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 84.
TCCR1B – Timer/Counter 1 Control Register B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x81) TCCR3B – Timer/Counter 3 Control Register B Bit 7 6 5 4 3 2 1 0 ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x91) TCCR4B – Timer/Counter 4 Control Register B Bit 7 6 5 4 3 2 1 0
ATmega640/1280/1281/2560/2561 • Bit 2:0 – CSn2:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 57 and Figure 58. Table 86. Clock Select Bit Description CSn2 CSn1 CSn0 Description 0 0 0 No clock source.
TCCR1C – Timer/Counter 1 Control Register C Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B FOC1C – – – – – Read/Write W W W R R R R R Initial Value 0 0 0 0 0 0 0 0 (0x82) TCCR3C – Timer/Counter 3 Control Register C Bit 7 6 5 4 3 2 1 0 FOC3A FOC3B FOC3C – – – – – Read/Write W W W R R R R R Initial Value 0 0 0 0 0 0 0 0 (0x92) TCCR4C – Timer/Counter 4 Control Register C Bit 7 6 5 4 3 2 1 0 FOC4A FOC4B FOC4C – – – – – Read/Write W W
ATmega640/1280/1281/2560/2561 TCNT1H and TCNT1L – Timer/Counter 1 TCNT3H and TCNT3L – Timer/Counter 3 TCNT4H and TCNT4L – Timer/Counter 4 TCNT5H and TCNT5L – Timer/Counter 5 Bit 7 6 5 4 3 (0x85) TCNT1[15:8] (0x84) TCNT1[7:0] 2 1 0 TCNT1H TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x95) TCNT3[15:8] (0x94) TCNT3[7:0] TCNT3H TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0
OCR1AH and OCR1AL – Output Compare Register 1 A OCR1BH and OCR1BL – Output Compare Register 1 B OCR1CH and OCR1CL – Output Compare Register 1 C OCR3AH and OCR3AL – Output Compare Register 3 A OCR3BH and OCR3BL – Output Compare Register 3 B OCR3CH and OCR3CL – Output Compare Register 3 C OCR4AH and OCR4AL – Output Compare Register 4 A OCR4BH and OCR4BL – Output Compare Register 4 B 166 Bit 7 6 5 4 3 (0x89) OCR1A[15:8] (0x88) OCR1A[7:0] 2 1 0 OCR1AH OCR1AL Read/Write R/W R/W R/W R/W
ATmega640/1280/1281/2560/2561 OCR4CH and OCR4CL – Output Compare Register 4 C OCR5AH and OCR5AL – Output Compare Register 5 A OCR5BH and OCR5BL – Output Compare Register 5 B OCR5CH and OCR5CL – Output Compare Register 5 C Bit 7 6 5 4 3 (0xAD) OCR4C[15:8] (0xAC) OCR4C[7:0] 2 1 0 OCR4CH OCR4CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x129) OCR5A[15:8] (0x128) OCR5A[7:0] OCR5AH OCR5AL Read/Write R/W R/W R/
ICR1H and ICR1L – Input Capture Register 1 ICR3H and ICR3L – Input Capture Register 3 – ICR4H and ICR4L – Input Capture Register 4 ICR5H and ICR5L – Input Capture Register 5 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x97) ICR3[15:8] (0x96) ICR3[7:0] ICR3H ICR3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0
ATmega640/1280/1281/2560/2561 TIMSK1 – Timer/Counter 1 Interrupt Mask Register TIMSK3 – Timer/Counter 3 Interrupt Mask Register TIMSK4 – Timer/Counter 4 Interrupt Mask Register TIMSK5 – Timer/Counter 5 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6F) – – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x71) – – ICIE3 – OCIE3C OCIE3B OCIE3A TOIE3 Read/Write R R R/W R R/W
TIFR1 – Timer/Counter1 Interrupt Flag Register TIFR3 – Timer/Counter3 Interrupt Flag Register TIFR4 – Timer/Counter4 Interrupt Flag Register TIFR5 – Timer/Counter5 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – OCF1C OCF1B OCF1A TOV1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x18 (0x38) – – ICF3 – OCF3C OCF3B OCF3A TOV3 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0
ATmega640/1280/1281/2560/2561 OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCFnA can be cleared by writing a logic one to its bit location. • Bit 0 – TOVn: Timer/Countern, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOVn Flag is set when the timer overflows. Refer to Table 82 on page 149 for the TOVn Flag behavior when using another WGMn3:0 bit setting.
Timer/Counter 0, 1, 3, 4, and 5 Prescaler Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or 5. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega640/1280/1281/2560/2561 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 62.
Output Compare Modulator (OCM1C0A) Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “Timer/Counter 0, 1, 3, 4, and 5 Prescaler” on page 172 and “8-bit Timer/Counter2 with PWM and Asynchronous Operation” on page 176. Figure 63.
ATmega640/1280/1281/2560/2561 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. Timing Example Figure 65 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 65.
8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
ATmega640/1280/1281/2560/2561 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
Figure 67. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value.
ATmega640/1280/1281/2560/2561 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output.
ATmega640/1280/1281/2560/2561 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three.
Phase Correct PWM Mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when MGM22:0 = 5.
ATmega640/1280/1281/2560/2561 between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
ATmega640/1280/1281/2560/2561 OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not.
port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 191.
ATmega640/1280/1281/2560/2561 Figure 74. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 75 shows the setting of OCF2A in all modes except CTC mode. Figure 75. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 76 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x. 4.
ATmega640/1280/1281/2560/2561 down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
Figure 77. Prescaler for Timer/Counter2 PSRASY clkT2S/1024 clkT2S/256 AS2 clkT2S/128 10-BIT T/C PRESCALER Clear clkT2S/64 TOSC1 clkT2S clkT2S/32 clkI/O clkT2S/8 Timer/Counter Prescaler 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
ATmega640/1280/1281/2560/2561 Register Description TCCR2A –Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior.
Table 90. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR2A equals TOP and COM2A1 is set.
ATmega640/1280/1281/2560/2561 Table 93 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 93. Compare Output Mode, Phase Correct PWM Mode(1) COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match when down-counting. 1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match when down-counting. Note: Description 1.
TCCR2B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
ATmega640/1280/1281/2560/2561 Table 95. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
ASSR – Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 (0xB6) – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal.
ATmega640/1280/1281/2560/2561 The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
ATmega640/1280/1281/2560/2561 SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices.
Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line.
ATmega640/1280/1281/2560/2561 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 96. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 89. Table 96. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega640/1280/1281/2560/2561 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega640/1280/1281/2560/2561 Table 97. CPOL Functionality Leading Edge Trailing eDge SPI Mode CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3 Figure 80.
Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled.
ATmega640/1280/1281/2560/2561 • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 100.
SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
ATmega640/1280/1281/2560/2561 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
Figure 82. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER UCSRB RxD UCSRC 1.
ATmega640/1280/1281/2560/2561 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA Register.
Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 83. The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRLn Register is written.
ATmega640/1280/1281/2560/2561 Some examples of UBRRn values for some system clock frequencies are found in Table 109 on page 232. Double Speed Operation (U2Xn) The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication.
Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit.
ATmega640/1280/1281/2560/2561 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization.
More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register.
ATmega640/1280/1281/2560/2561 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
ATmega640/1280/1281/2560/2561 Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done.
Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
ATmega640/1280/1281/2560/2561 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e.
ATmega640/1280/1281/2560/2561 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver.
are emphasized on the figure by having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit.
ATmega640/1280/1281/2560/2561 Table 102 and Table 103 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 102. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.
Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
ATmega640/1280/1281/2560/2561 Register Description UDRn – USART I/O Data Register n The following section describes the USART’s registers. Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
• Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
ATmega640/1280/1281/2560/2561 • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled.
• Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 105.
ATmega640/1280/1281/2560/2561 • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 108.
Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 109 to Table 112. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega640/1280/1281/2560/2561 Table 110. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.
Table 111. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.
ATmega640/1280/1281/2560/2561 Table 112. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.
USART in SPI Mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation.
ATmega640/1280/1281/2560/2561 The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 113: Table 113.
Figure 89. UCPHAn and UCPOLn data transfer timing diagrams. UCPHA=0 UCPHA=1 UCPOL=0 Frame Formats UCPOL=1 XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) A serial frame for the MSPIM is defined to be one character of 8 data bits.
ATmega640/1280/1281/2560/2561 enabled). The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
USART MSPIM Register Description The following section describes the registers used for SPI operation using the USART. UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “UDRn – USART I/O Data Register n” on page 227.
ATmega640/1280/1281/2560/2561 UCSRnB – USART MSPIM Control and Status Register n B Bit 7 6 5 4 3 2 1 RXCIEn TXCIEn UDRIE RXENn TXENn - - 0 - Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag.
UCSRnC – USART MSPIM Control and Status Register n C Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC • Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in Table 115. See “UCSRnC – USART Control and Status Register n C” on page 229 for full description of the normal USART operation.
ATmega640/1280/1281/2560/2561 2-wire Serial Interface Features • • • • • • • • • • 2-wire Serial Interface Bus Definition The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
Electrical Interconnection As depicted in Figure 90, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
ATmega640/1280/1281/2560/2561 Figure 92. START, REPEATED START and STOP conditions SDA SCL START Address Packet Format STOP REPEATED START START STOP All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
ATmega640/1280/1281/2560/2561 Multi-master Bus The TWI protocol allows bus systems with several masters. Special concerns have Systems, Arbitration and been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-masSynchronization ter systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
Figure 97. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
ATmega640/1280/1281/2560/2561 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 98. All registers drawn in a thick line are accessible through the AVR data bus. Figure 98.
CPU Clock frequency SCL frequency = ----------------------------------------------------------TWPS 16 + 2(TWBR) ⋅ 4 • TWBR = Value of the TWI Bit Rate Register. • TWPS = Value of the prescaler bits in the TWI Status Register. Note: Bus Interface Unit Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See “2-wire Serial Interface Characteristics” on page 379 for value of pull-up resistor.
ATmega640/1280/1281/2560/2561 Using the TWI • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed by own slave address or general call. • After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition. The AVR TWI is byte-oriented and interrupt based.
TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. 3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted.
ATmega640/1280/1281/2560/2561 • When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle. • After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag.
Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
ATmega640/1280/1281/2560/2561 Figure 100. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 118.
ATmega640/1280/1281/2560/2561 Figure 101.
Figure 102. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ R1 Device n R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
ATmega640/1280/1281/2560/2561 START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 119.
Figure 103.
ATmega640/1280/1281/2560/2561 The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
Table 120.
ATmega640/1280/1281/2560/2561 Figure 105. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 106). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 106. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER ........
ATmega640/1280/1281/2560/2561 In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared (by writing it to one).
Figure 107. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
ATmega640/1280/1281/2560/2561 Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2. The EEPROM must be instructed what location should be read. 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa.
• Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
ATmega640/1280/1281/2560/2561 Register Description TWBR – TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB8) TWBR • Bits 7:0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.
ATmega640/1280/1281/2560/2561 • Bits 1:0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 123. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator Unit” on page 251. The value of TWPS1:0 is used in the equation.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. TWAMR – TWI (Slave) Address Mask Register Bit 7 6 5 4 3 2 1 0 TWAM[6:0] (0xBD) – Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TWAMR • Bits 7:1 – TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask.
ATmega640/1280/1281/2560/2561 AC – Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Analog Comparator Multiplexed Input It is possible to select any of the ADC15:0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature.
ATmega640/1280/1281/2560/2561 Register Description ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – MUX5 ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists.
ATmega640/1280/1281/2560/2561 ADC – Analog to Digital Converter Features • • • • • • • • • • • • • • • 10-bit Resolution 1 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 - 260 µs Conversion Time Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution) 16 Multiplexed Single Ended Input Channels 14 Differential input channels 4 Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.
Figure 113. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] ADFR ADSC TRIGGER SELECT AREF ADC[9:0] ADIF ADPS[2:0] ADEN MUX[5] DIFF / GAIN SELECT CHANNEL SELECTION INTERNAL REFERENCE (1.1V/2.
ATmega640/1280/1281/2560/2561 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V or 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register.
Figure 114. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATmega640/1280/1281/2560/2561 setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles.
Figure 117. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 118.
ATmega640/1280/1281/2560/2561 Table 126. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.5 13/14 Condition Auto Triggered conversions Normal conversions, differential Differential Channels When using differential channels, certain aspects of the conversion need to be taken into consideration.
Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
ATmega640/1280/1281/2560/2561 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 1.1V reference, internal 2.56V reference or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier.
Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 120. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
ATmega640/1280/1281/2560/2561 Figure 121. ADC Power Connections, ATmega1281/2561. PA0 VCC 10υΗ 51 52 GND 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 GND AVCC 63 64 100nF 1 PG5 Ground Plane Figure 122.
Offset Compensation Schemes The stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB.
ATmega640/1280/1281/2560/2561 • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 125. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB).
ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 128 on page 294 and Table 129 on page 295). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega640/1280/1281/2560/2561 Table 127. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding Decimal Value VADCm + VREF / GAIN 0x1FF 511 VADCm + 0.999 VREF / GAIN 0x1FF 511 VADCm + 0.998 VREF / GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF / GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF / GAIN 0x3FF -1 ... ... ... VADCm - 0.999 VREF / GAIN 0x201 -511 VADCm - VREF / GAIN 0x200 -512 Example: ADMUX = 0xFB (ADC3 - ADC2, 10x gain, 2.
Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 128. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
ATmega640/1280/1281/2560/2561 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – MUX5 ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 3 – MUX5: Analog Channel and Gain Selection Bit This bit is used together with MUX4:0 in ADMUX to select which combination in of analog inputs are connected to the ADC. See Table 129 for details.
Table 129. Input Channel Selections (Continued) Positive Differential Input Negative Differential Input Gain ADC2 ADC2 1x ADC3 ADC2 1x 011100 ADC4 ADC2 1x 011101 ADC5 ADC2 1x MUX5:0 Single Ended Input 011010 011011 N/A 011110 1.
ATmega640/1280/1281/2560/2561 Table 129. Input Channel Selections (Continued) MUX5:0 Single Ended Input 111101 N/A 111110 Reserved N/A 111111 Reserved N/A Note: ADCSRA – ADC Control and Status Register A Positive Differential Input Negative Differential Input Gain ADC13 ADC10 1x 1. To reach the given accuracy, 10x or 200x Gain should not be used for operating voltage below 2.
Table 130.
ATmega640/1280/1281/2560/2561 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – MUX5 ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7 – Res: Reserved Bit This bit is reserved for future use. To ensure compatibility with future devices, this bit must be written to zero when ADCSRB is written.
DIDR0 – Digital Input Disable Register 0 Bit 7 6 5 4 3 2 1 0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7E) DIDR0 • Bit 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
ATmega640/1280/1281/2560/2561 JTAG Interface and On-chip Debug System Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
Figure 128.
ATmega640/1280/1281/2560/2561 TAP - Test Access Port The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are: • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. • TCK: Test Clock. JTAG operation is synchronous to TCK. • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out.
TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 129 depend on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-Logic-Reset. As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
ATmega640/1280/1281/2560/2561 Using the Boundaryscan Chain A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 308. Using the On-chip Debug As shown in Figure 128, the hardware support for On-chip Debugging consists mainly of System • A scan chain on the interface between the internal AVR CPU and the internal peripheral units. • Break Point unit. • Communication interface between the CPU and JTAG system.
On-chip Debug Specific JTAG Instructions The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference. PRIVATE0; 0x8 Private JTAG instruction for accessing On-chip debug system. PRIVATE1; 0x9 Private JTAG instruction for accessing On-chip debug system. PRIVATE2; 0xA Private JTAG instruction for accessing On-chip debug system.
ATmega640/1280/1281/2560/2561 On-chip Debug Related Register in I/O Memory OCDR – On-chip Debug Register Bit 7 6 5 4 3 2 1 0 0x31 (0x51) MSB/IDRD LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
IEEE 1149.1 (JTAG) Boundary-scan Features • • • • • System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register.
ATmega640/1280/1281/2560/2561 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register Figure 130 shows the structure of the Device Identification Register. Figure 130.
Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 311 for a complete description. Boundary-scan Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation.
ATmega640/1280/1281/2560/2561 The active states are: • BYPASS; 0xF Shift-DR: The Reset Register is shifted by the TCK input. Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states are: • Capture-DR: Loads a logic “0” into the Bypass Register. • Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
Figure 132. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
ATmega640/1280/1281/2560/2561 Figure 133.
Boundary-scan Related Register in I/O Memory MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled.
ATmega640/1280/1281/2560/2561 ATmega640/1280/1281/25 Table 132 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit 60/2561 Boundary-scan scanned out. The scan order follows the pin-out order as far as possible. Therefore, the Order bits of Port A and Port K is scanned in the opposite bit order of the other ports.
Table 132. ATmega640/1280/2560 Boundary-scan Order (Continued) 316 Bit Number Signal Name Module 140 PH3.Data 139 PH3.Control 138 PH4.Data 137 PH4.Control 136 PH5.Data 135 PH5.Control 134 PH6.Data 133 PH6.Control 132 PB0.Data 131 PB0.Control 130 PB1.Data 129 PB1.Control 128 PB2.Data 127 PB2.Control 126 PB3.Data 125 PB3.Control 124 PB4.Data 123 PB4.Control 122 PB5.Data 121 PB5.Control 120 PB6.Data 119 PB6.Control 118 PB7.Data 117 PB7.Control 116 PH7.
ATmega640/1280/1281/2560/2561 Table 132. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 104 PL2.Control 103 PL3.Data 102 PL3.Control 101 PL4.Data 100 PL4.Control 99 PL5.Data 98 PL5.Control 97 PL6.Data 96 PL6.Control 95 PL7.Data 94 PL7.Control 93 PD0.Data 92 PD0.Control 91 PD1.Data 90 PD1.Control 89 PD2.Data 88 PD2.Control 87 PD3.Data 86 PD3.Control 85 PD4.Data 84 PD4.Control 83 PD5.Data 82 PD5.Control 81 PD6.Data 80 PD6.
Table 132. ATmega640/1280/2560 Boundary-scan Order (Continued) 318 Bit Number Signal Name 68 PC2.Control 67 PC3.Data 66 PC3.Control 65 PC4.Data 64 PC4.Control 63 PC5.Data 62 PC5.Control 61 PC6.Data 60 PC6.Control 59 PC7.Data 58 PC7.Control 57 PJ0.Data 56 PJ0.Control 55 PJ1.Data 54 PJ1.Control 53 PJ2.Data 52 PJ2.Control 51 PJ3.Data 50 PJ3.Control 49 PJ4.Data 48 PJ4.Control 47 PJ5.Data 46 PJ5.Control 45 PJ6.Data 44 PJ6.Control 43 PG2.Data 42 PG2.
ATmega640/1280/1281/2560/2561 Table 132. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 32 PA3.Control 31 PA2.Data 30 PA2.Control 29 PA1.Data 28 PA1.Control 27 PA0.Data 26 PA0.Control 25 PJ7.Data 24 PJ7.Control 23 PK7.Data 22 PK7.Control 21 PK6.Data 20 PK6.Control 19 PK5.Data 18 PK5.Control 17 PK4.Data 16 PK4.Control 15 PK3.Data 14 PK3.Control 13 PK2.Data 12 PK2.Control 11 PK1.Data 10 PK1.Control 9 PK0.Data 8 PK0.Control 7 PF3.
Table 133. ATmega1281/2561 Boundary-scan Order 320 Bit Number Signal Name Module 100 PG5.Data Port G 99 PG5.Control 98 PE0.Data 97 PE0.Control 96 PE1.Data 95 PE1.Control 94 PE2.Data 93 PE2.Control 92 PE3.Data 91 PE3.Control 90 PE4.Data 89 PE4.Control 88 PE5.Data 87 PE5.Control 86 PE6.Data 85 PE6.Control 84 PE7.Data 83 PE7.Control 82 PB0.Data 81 PB0.Control 80 PB1.Data 79 PB1.Control 78 PB2.Data 77 PB2.Control 76 PB3.Data 75 PB3.Control 74 PB4.
ATmega640/1280/1281/2560/2561 Table 133. ATmega1281/2561 Boundary-scan Order (Continued) Bit Number Signal Name Module 65 PG3.Control 64 PG4.Data 63 PG4.Control 62 RSTT Reset Logic (Observe Only) 61 PD0.Data Port D 60 PD0.Control 59 PD1.Data 58 PD1.Control 57 PD2.Data 56 PD2.Control 55 PD3.Data 54 PD3.Control 53 PD4.Data 52 PD4.Control 51 PD5.Data 50 PD5.Control 49 PD6.Data 48 PD6.Control 47 PD7.Data 46 PD7.Control 45 PG0.Data 44 PG0.Control 43 PG1.
Table 133. ATmega1281/2561 Boundary-scan Order (Continued) 322 Bit Number Signal Name 29 PC6.Data 28 PC6.Control 27 PC7.Data 26 PC7.Control 25 PG2.Data 24 PG2.Control 23 PA7.Data 22 PA7.Control 21 PA6.Data 20 PA6.Control 19 PA5.Data 18 PA5.Control 17 PA4.Data 16 PA4.Control 15 PA3.Data 14 PA3.Control 13 PA2.Data 12 PA2.Control 11 PA1.Data 10 PA1.Control 9 PA0.Data 8 PA0.Control 7 PF3.Data 6 PF3.Control 5 PF2.Data 4 PF2.Control 3 PF1.Data 2 PF1.
ATmega640/1280/1281/2560/2561 Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
• When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation. Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
ATmega640/1280/1281/2560/2561 Figure 135. Read-While-Write vs.
Figure 136.
ATmega640/1280/1281/2560/2561 Table 135. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section.
Addressing the Flash During SelfProgramming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Zregisters ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is implementation dependent. Note that the RAMPZ register is only implemented when the program space is larger than 64K bytes.
ATmega640/1280/1281/2560/2561 Alternative 1, fill the buffer before a Page Erase • Fill temporary page buffer • Perform a Page Erase • Perform a Page Write Alternative 2, fill the buffer after Page Erase • Perform a Page Erase • Fill temporary page buffer • Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten.
accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 69. Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible.
ATmega640/1280/1281/2560/2561 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register.
CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Table 138. Signature Row Addressing Signature Byte Device Signature Byte 1 0x0000 Device Signature Byte 2 0x0002 Device Signature Byte 3 0x0004 RC Oscillator Calibration Byte 0x0001 Note: Preventing Flash Corruption Z-Pointer Address All other addresses are reserved for future use.
ATmega640/1280/1281/2560/2561 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega640/1280/1281/2560/2561 ATmega640 Boot Loader Parameters In Table 140 through Table 142, the parameters used in the description of the Self-Programming are given. Boot Reset Address (Start Boot Loader Section) End Application Section Boot Loader Flash Section Appli-cation Flash Section Pages Boot Size BOOTSZ0 BOOTSZ1 Table 140.
Table 142. Explanation of different variables used in Figure 137 and the mapping to the Z-pointer, ATmega640 Corresponding Z-value(2) Variable PAGEMSB Most significant bit which is used to address the words within one page (128 words in a page requires seven bits PC [6:0]). ZPCMSB Z15 Bit in Z-pointer that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1. ZPAGEMS B Z7 Bit in Z-pointer that is mapped to PCMSB. Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1.
ATmega640/1280/1281/2560/2561 Table 144. Read-While-Write Limit, ATmega1280/1281 Section(1) Pages Address Read-While-Write section (RWW) 480 0x0000 - 0xEFFF No Read-While-Write section (NRWW) 32 0xF000 - 0xFFFF Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page 324 and “RWW – Read-While-Write Section” on page 324. Table 145.
ATmega2560/2561 Boot Loader Parameters In Table 146 through Table 148, the parameters used in the description of the Self-Programming are given. Boot Reset Address (Start Boot Loader Section) End Application Section Boot Loader Flash Section Appli-cation Flash Section Pages Boot Size BOOTSZ0 BOOTSZ1 Table 146.
ATmega640/1280/1281/2560/2561 Table 148. Explanation of different variables used in Figure 137 and the mapping to the Z-pointer, ATmega2560/2561 Corresponding Z-value(2) Variable Description(1) PCMSB 16 Most significant bit in the Program Counter. (The Program Counter is 17 bits PC[16:0]) PAGEMSB 6 Most significant bit which is used to address the words within one page (128 words in a page requires seven bits PC [6:0]).
Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega640/1280/1281/2560/2561 • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
Memory Programming Program And Data Memory Lock Bits The ATmega640/1280/1281/2560/2561 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 150. The Lock bits can only be erased to “1” with the Chip Erase command. Table 149.
ATmega640/1280/1281/2560/2561 Table 150. Lock Bit Protection Modes(1)(2) (Continued) Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
Table 152. Fuse High Byte Fuse High Byte Bit No Description Default Value Enable OCD 1 (unprogrammed, OCD disabled) Enable JTAG 0 (programmed, JTAG enabled) OCDEN(4) 7 JTAGEN 6 SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega640/1280/1281/2560/2561 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
When pulsing WR or OE, the command loaded determines the action executed. The different commands are shown in Table 161. Figure 138. Parallel Programming(1) +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V VCC +5V AVCC PB7 - PB0 DATA RESET BS2 PA0 XTAL1 GND Note: 1. Unused Pins should be left floating. Table 157.
ATmega640/1280/1281/2560/2561 Table 158. BS2 and BS1 Encoding BS2 BS1 Flash / EEPROM Address Flash Data Loading / Reading Fuse Programming Reading Fuse and Lock Bits 0 1 High Byte High Byte High Byte Lockbits 1 0 Extended High Byte Reserved Extended Byte Extended Fuse Byte 1 1 Reserved Reserved Reserved Fuse High Byte , Table 159.
Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 159 on page 347 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5.
ATmega640/1280/1281/2560/2561 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “00”. This selects the address low byte. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2.
1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 139. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1.
ATmega640/1280/1281/2560/2561 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF). 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS2, BS1 to “00”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3.
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 348 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
ATmega640/1280/1281/2560/2561 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 348 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 348 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. Parallel Programming Characteristics Figure 144.
ATmega640/1280/1281/2560/2561 Figure 146. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 144 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 162.
Table 162. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Serial Downloading Serial Programming Pin Mapping Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
ATmega640/1280/1281/2560/2561 When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present.
Flash memory, use the instruction Load Extended Address Byte to define the upper address byte, which is not included in the Read Program Memory instruction. The extended address byte is stored until the command is re-issued, i.e., the command needs only be issued for the first page, and when crossing the 64KWord boundary. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 164.
ATmega640/1280/1281/2560/2561 Serial Programming Instruction set Table 165 on page 359 and Figure 148 on page 360 describes the Instruction set. Table 165.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 148 on page 360. Figure 148.
ATmega640/1280/1281/2560/2561 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Figure 150. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR AVR_RESET (0xC) 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
ATmega640/1280/1281/2560/2561 PROG_COMMANDS (0x5) PROG_PAGELOAD (0x6) PROG_PAGEREAD (0x7) Data Registers The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register.
Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega640/1280/1281/2560/2561 Figure 152.
Table 166. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
ATmega640/1280/1281/2560/2561 Table 166. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c.
Table 166. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 8d. Read Fuse Low Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
ATmega640/1280/1281/2560/2561 Figure 153.
including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 154. Flash Data Byte Register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK.
ATmega640/1280/1281/2560/2561 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 370. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address Extended High byte using programming instruction 2b. 4. Load address High byte using programming instruction 2c. 5. Load address Low byte using programming instruction 2d. 6. Load data using programming instructions 2e, 2f and 2g. 7.
5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6.
ATmega640/1280/1281/2560/2561 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 162 on page 355).
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega640/1280/1281/2560/2561 TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Typ. Max.(5) Units Active 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 0.5 0.8 mA Active 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 3.2 5 mA Active 8MHz, VCC = 5V (ATmega640/1280/1281/2560/2561) 10 14 mA Idle 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 0.14 0.22 mA Idle 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 0.7 1.
4)The sum of all IOH, for ports E0-E7, G5 should not exceed 100 mA. 5)The sum of all IOH, for ports F0-F7, K0-K7 should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology.
ATmega640/1280/1281/2560/2561 Maximum speed vs. VCC Maximum frequency is depending on VCC. As shown in Figure 156 trough Figure 159, the Maximum Frequency vs. V CC curve is linear between 1.8V < V CC < 2.7V and between 2.7V < VCC < 4.5V. 8 MHz Figure 156. Maximum Frequency vs. VCC, ATmega640V/1280V/1281V/2560V/2561V 8 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 157. Maximum Frequency vs.
16 MHz Figure 158. Maximum Frequency vs. VCC, ATmega640/ATmega1280/ATmega1281 16 MHz 8 MHz Safe Operating Area 2.7V 4.5V 5.5V Figure 159. Maximum Frequency vs. VCC, ATmega2560/ATmega2561 16 MHz Safe Operating Area 4.5V 378 5.
ATmega640/1280/1281/2560/2561 2-wire Serial Interface Characteristics T a b l e 1 6 8 d e s c r i b e s t h e r e q u i r e m e n t s f o r d ev i c e s c o n n e c t e d t o t h e 2 - w i r e S e r i a l B u s . T h e ATmega640/1280/1281/2560/2561 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 160. Table 168. 2-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) VOL(1) Min Max Units Input Low-voltage -0.5 0.
4. fCK = CPU clock frequency 5. This requirement applies to all ATmega640/1280/1281/2560/2561 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz. 7.
ATmega640/1280/1281/2560/2561 Figure 161. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) MSB ... LSB Figure 162. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ADC Characteristics – Preliminary Data Table 170. ADC Characteristics, Singel Ended Channels Symbol Typ(1) Max(1) Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC= 200 kHz 2.25 (2) Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 1 MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 200 kHz Noise Reduction Mode 2 LSB Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC = 1 MHz Noise Reduction Mode 3 (2.
ATmega640/1280/1281/2560/2561 Table 171.
Table 171. ADC Characteristics, Differential Channels (Continued) Symbol Parameter Condition Min(1) Typ(1) Max(1) Units AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V VREF Reference Voltage 2.7(2.0) AVCC - 0.5 V GND VCC V Input Differential Voltage -VREF/Gain VREF/Gain V ADC Conversion Output -511 511 LSB VIN VDIFF Input Voltage Input Bandwidth 4 VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Note: 2.
ATmega640/1280/1281/2560/2561 External Data Memory Timing Table 173. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state 8 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 ns 2 tAVLL Address Valid A to ALE Low 57.5 0.
Table 175. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns 15 tDVWH Data Valid to WR High 375 3.0tCLCL ns 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns 325 3.0tCLCL-50 ns Table 176. External Data Memory Characteristics, 4.5 - 5.
ATmega640/1280/1281/2560/2561 Table 177. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued) 4 MHz Oscillator 12 Symbol Parameter Min tRLRH RD Pulse Width 235 Max Variable Oscillator Min Max 1.0tCLCL-15 Unit ns (1) 13 tDVWL Data Setup to WR Low 105 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 250 1.0tCLCL ns 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 ns Notes: 0.5tCLCL-20 ns 1.
Figure 163. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 T4 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 3a DA7:0 Prev. data Address 13 XX Data 14 16 6 Write 2 WR 3b DA7:0 (XMBK = 0) 11 9 Data 5 Read Address 10 8 12 RD Figure 164. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 3a DA7:0 Prev.
ATmega640/1280/1281/2560/2561 Figure 165. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T5 T4 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Address 11 5 Read Data 10 8 12 RD Figure 166. External Memory Timing (SRWn1 = 1, SRWn0 = 1)() T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 3a DA7:0 Prev.
Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
ATmega640/1280/1281/2560/2561 Figure 168. Active Supply Current vs. Frequency (1 - 16 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 16 MHz 25 5.5V 5.0V 20 ICC (m A) 4.5V 15 4.0V 10 3.3V 2.7V 5 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 169. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs.
Figure 170. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 2,5 -40˚C 85˚C 25˚C 2 ICC (mA) 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 171. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs.
ATmega640/1280/1281/2560/2561 Idle Supply Current Figure 172. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,6 5.5V 0,5 5.0V ICC (mA) 0,4 4.5V 4.0V 0,3 3.3V 0,2 2.7V 1.8V 0,1 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 173. Idle Supply Current vs. Frequency (1 - 16 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 16 MHz 8 7 5.5V 6 5.0V ICC (mA) 5 4.5V 4 4.0V 3 2 3.3V 2.7V 1 1.
Figure 174. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 3,5 85˚C 25˚C -40˚C 3 ICC (mA) 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 175. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs.
ATmega640/1280/1281/2560/2561 Figure 176. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz)I IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 0,3 -40˚C 0,25 ICC (mA) 0,2 25˚C 0,15 85˚C 0,1 0,05 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Supply Current of IO modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
Table 181. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRTIM0 4.0 uA 24 uA 100 uA PRSPI 15 uA 95 uA 400 uA PRADC 12 uA 75 uA 315 uA Table 182. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock Additional Current consumption compared to Idle with external clock PRUSART3 3.
ATmega640/1280/1281/2560/2561 Power-down Supply Current Figure 177. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 4 85˚C 3,5 3 ICC (uA) 2,5 2 1,5 -40˚C 25˚C 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 178. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs.
Power-save Supply Current Figure 179. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 4 3,5 25 ˚C 3 I CC (uA) 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 180. Power-save Supply Current vs. VCC (Watchdog Timer Enabled) POWER-SAVE SUPPLY CURRENT vs.
ATmega640/1280/1281/2560/2561 Standby Supply Current Figure 181. Standby Supply Current vs. VCC (Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 0,2 6 MHz xtal 6 MHz res 0,18 0,16 ICC (m A) 0,14 4 MHz res 4 MHz xtal 0,12 0,1 0,08 2 MHz res 2 MHz xtal 0,06 1 MHz res 455 kHz res 0,04 0,02 32 kHz xtal 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Pin Pull-up Figure 182. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.
Figure 183. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 90 80 70 IOP (uA) 60 50 40 30 20 85˚C 25˚C -40˚C 10 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 184. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
ATmega640/1280/1281/2560/2561 Figure 185. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 IRESET(uA) 30 25 20 15 10 25˚C -40˚C 85˚C 5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET(V) Figure 186. Reset pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc= 2.
Figure 187. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE V CC = 5V 120 100 IRESET(uA) 80 60 40 20 25˚C -40˚C 85˚C 0 0 1 2 3 4 5 6 VRESET(V) Pin Driver Strength Figure 188. I/O Pin output Voltage vs.Sink Current (VCC = 3 V) I/O PIN OUTPUT VOLTAGE vs.
ATmega640/1280/1281/2560/2561 Figure 189. I/O Pin Output Voltage vs. Sink Current (VCC = 5 V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0,6 85˚C 0,5 25˚C -40˚C VOL (V) 0,4 0,3 0,2 0,1 0 0 5 10 15 20 25 IOL (mA) Figure 190. I/O Pin Output Voltage vs. Source Current (VCC = 3 V) I/O PIN OUTPUT VOLTAGE vs.
Figure 191. I/O Pin Output Voltage vs. Source Current (VCC = 5 V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5,1 5 4,9 VOH (V) 4,8 4,7 4,6 -40˚C 4,5 25˚C 4,4 85˚C 4,3 0 5 10 15 20 25 IOH (mA) Pin Threshold and Hysteresis Figure 192. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) I/O PIN INPUT THRESHOLD VOLTAGE vs.
ATmega640/1280/1281/2560/2561 Figure 193. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2,5 85˚C 25˚C -40˚C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 194. I/O Pin Input Hysteresis I/O PIN INPUT HYSTERESIS vs.
Figure 195. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) RESET INPUT THRESHOLD VOLTAGE vs. V CC VIH, IO PIN READ AS '1' 2,5 -40˚C 25˚C 85˚C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 196. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) RESET INPUT THRESHOLD VOLTAGE vs.
ATmega640/1280/1281/2560/2561 Figure 197. Reset Pin Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 0,7 Input Hysteresis(mV) 0,6 0,5 0,4 0,3 0,2 0,1 -40˚C 25˚C 85˚C 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 80 100 VCC (V) BOD Threshold and Analog Comparator Offset Figure 198. BOD Threshold vs. Temperature (BOD Level is 4.3 V) BOD THRESHOLDS vs. TEMPERATURE BODLEVELS IS 4.3V 4.4 4.35 Threshold (V) Rising Vcc 4.3 4.25 Falling Vcc 4.
Figure 199. BOD Threshold vs. Temperature (BOD Level is 2.7 V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.8 Rising Vcc Threshold (V) 2.75 2.7 Falling Vcc 2.65 2.6 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 200. BOD Threshold vs. Temperature (BOD Level is 1.8 V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V 1.9 1.85 Threshol d ( V) Rising Vcc 1.8 Fallling Vcc 1.75 1.
ATmega640/1280/1281/2560/2561 Internal Oscillator Speed Figure 201. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 128 126 -40˚C FRC (kHz) 124 25 ˚C 122 120 118 116 85˚C 114 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 202. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 128 126 FRC (kHz) 124 122 120 2.1V 2.7V 3.3V 4.0V 5.
Figure 203. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 8,3 85˚C 8,2 FRC (MHz) 8,1 25˚C 8 7,9 -40˚C 7,8 7,7 7,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 204. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8,5 5.0V 8,4 3.
ATmega640/1280/1281/2560/2561 Figure 205. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 85˚C 25˚C -40˚C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 206. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs.
Figure 207. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AV CC 350 -40˚C 25˚C 85˚C 300 ICC (uA) 250 200 150 100 50 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 208. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs.
ATmega640/1280/1281/2560/2561 Figure 209. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. V CC 9 -40˚C 8 25˚C 7 85˚C ICC (uA) 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 210. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs.
Figure 211. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 16 -40 ˚C 14 ICC (mA) 12 25 ˚C 10 8 85 ˚C 6 4 2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 212. Reset Supply Current vs VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 0,35 5.5V 0,3 5.0V 0,25 ICC (mA) 4.5V 0,2 4.0V 0,15 3.3V 0,1 2.7V 1.
ATmega640/1280/1281/2560/2561 Figure 213. Reset Supply Current vs. VCC (1 - 16 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. V CC 1 - 16 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 4 5.5V 3,5 5.0V 3 ICC (mA) 4.5V 2,5 2 4.0V 1,5 1 3.3V 2.7V 0,5 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 214. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs.
Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x1FF) Reserved - - - - - - - - - - - - - - - - - - - ...
ATmega640/1280/1281/2560/2561 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x101) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 page 117 (0x100) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 page 117 (0xFF) Reserved - - - - - - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - - (0xFA) Reserved - - - - - - - -
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBF) Reserved - - - - - - - - Page (0xBE) Reserved - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 (0xB8) TWBR (0xB7) Reserved - - - - - - - - (0xB6) ASSR - EXCLK AS2 TC
ATmega640/1280/1281/2560/2561 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7D) DIDR2 ADC15D ADC14D ADC13D ADC12D ADC11D ADC10D ADC9D ADC8D page 300 (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 294 (0x7B) ADCSRB - ACME - - MUX5 ADTS2 ADTS1 ADTS0 page 277,295,,299 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH (0x78) ADCL (0x77) Reserved (0x76) (0x75) ADC Data Register High byte page 29
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1B (0x3B) PCIFR - - - - - PCIF2 PCIF1 PCIF0 page 81 0x1A (0x3A) TIFR5 - - ICF5 - OCF5C OCF5B OCF5A TOV5 page 169 0x19 (0x39) TIFR4 - - ICF4 - OCF4C OCF4B OCF4A TOV4 page 170 0x18 (0x38) TIFR3 - - ICF3 - OCF3C OCF3B OCF3A TOV3 page 170 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 page 197 0x16 (0x36) TIFR1 - - ICF1 - OCF1C OCF1B OCF1A TOV1 page 170 0x15 (0x35) TIFR
ATmega640/1280/1281/2560/2561 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subt
Mnemonics Operands Description Operation Flags #Clocks BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in
ATmega640/1280/1281/2560/2561 Mnemonics ELPM Operands Rd, Z+ SPM Description Operation Flags #Clocks Extended Load Program Memory Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1 None Store Program Memory (Z) ← R1:R0 None - Rd ← P None 1 3 IN Rd, P In Port OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 None 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr.
Ordering Information ATmega640 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) 1.8 - 5.5V ATmega640V-8AU ATmega640V-8CU 100A 100C1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega640-16AU ATmega640-16CU 100A 100C1 Industrial (-40°C to 85°C) Operation Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Maximum speed vs. VCC” on page 377. 3.
ATmega640/1280/1281/2560/2561 ATmega1281 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) Operation Range 1.8 - 5.5V ATmega1281V-8AU ATmega1281V-8MU 64A 64M2 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega1281-16AU ATmega1281-16MU 64A 64M2 Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Maximum speed vs. VCC” on page 377. 3.
ATmega1280 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) 1.8 - 5.5V ATmega1280V-8AU ATmega1280V-8CU 100A 100C1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega1280-16AU ATmega1280-16AU 100A 100C1 Industrial (-40°C to 85°C) Operation Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Maximum speed vs. VCC” on page 377. 3.
ATmega640/1280/1281/2560/2561 ATmega2561 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) Operation Range 1.8 - 5.5V ATmega2561V-8AU ATmega2561V-8MU 64A 64M2 Industrial (-40°C to 85°C) 4.5 - 5.5V ATmega2561-16AU ATmega2561-16MU 64A 64M2 Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Maximum speed vs. VCC” on page 377. 3.
ATmega2560 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) 1.8 - 5.5V ATmega2560V-8AU ATmega2560V-8CU 100A 100C1 Industrial (-40°C to 85°C) 4.5 - 5.5V ATmega2560-16AU ATmega2560-16CU 100A 100C1 Industrial (-40°C to 85°C) Operation Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See “Maximum speed vs. VCC” on page 377. 3.
ATmega640/1280/1281/2560/2561 Packaging Information 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.
100C1 0.12 Z E Marked A1 Identifier SIDE VIEW D A TOP VIEW A1 Øb e A1 Corner 0.90 TYP 10 9 8 7 6 5 4 3 2 1 A 0.90 TYP B C D COMMON DIMENSIONS (Unit of Measure = mm) E D1 F e SYMBOL MIN NOM MAX H A 1.10 – 1.20 I A1 0.30 0.35 0.40 D 8.90 9.00 9.10 E 8.90 9.00 9.10 G J E1 BOTTOM VIEW D1 7.10 7.20 7.30 E1 7.10 7.20 7.30 Øb 0.35 0.40 0.45 e NOTE 0.
ATmega640/1280/1281/2560/2561 64A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
64M2 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 – 0.02 0.05 0.18 0.25 0.30 A1 b K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW D 8.90 9.00 9.10 D2 7.50 7.65 7.80 E 8.90 9.00 9.10 E2 7.50 7.65 7.80 e NOTE 0.50 BSC L 0.35 0.40 0.45 K 0.20 0.27 0.
ATmega640/1280/1281/2560/2561 Errata ATmega640 rev. A • Inaccurate ADC conversion in differential mode with 200x gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200x gain With AVCC < 3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None 2. High current consumption in sleep mode.
ATmega1281 rev. A • Inaccurate ADC conversion in differential mode with 200x gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200x gain With AVCC < 3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None 2. High current consumption in sleep mode.
ATmega640/1280/1281/2560/2561 ATmega2560 rev. A • • • • • • 1. Non-Read-While-Write area of flash not functional Part does not work under 2.4 volts Incorrect ADC reading in differential mode Internal ADC reference has too low value IN/OUT instructions may be executed twice when Stack is in external RAM EEPROM read from application code does not work in Lock Bit Mode 3 Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected.
6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. ATmega2561 rev. E No known errata. ATmega2561 rev. D Not sampled. ATmega2561 rev. C • High current consumption in sleep mode 1. High current consumption in sleep mode.
ATmega640/1280/1281/2560/2561 2. Part does not work under 2.4 volts The part does not execute code correctly below 2.4 volts Problem Fix/Workaround Do not use the part at voltages below 2.4 volts. 3. Incorrect ADC reading in differential mode The ADC has high noise in differential mode. It can give up to 7 LSB error. Problem Fix/Workaround Use only the 7 MSB of the result when using the ADC in differential mode 4.
Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. Rev. 2549K-01/07 1. 2. 3. 4. 5. 6: 7. 8. 9. 10. Updated Table 1 on page 3. Updated “Pin Descriptions” on page 7. Updated “Stack Pointer” on page 14. Updated “Bit 1 – EEPE: EEPROM Programming Enable” on page 33. Updated Assembly code example in “Watchdog Timer” on page 62.
ATmega640/1280/1281/2560/2561 8. 9. 10. Updated “Ordering Information” on page 424. Added Package information “100C1” on page 430. Updated “Errata” on page 433. 1. Updated Figure 15 on page 28, Figure 16 on page 29 and Figure 17 on page 29. Updated Table 88 on page 191 and Table 89 on page 191. Updated Features in “ADC – Analog to Digital Converter” on page 279. Updated “Fuse Bits” on page 343. Rev. 2549F-04/06 2. 3. 4. Rev. 2549E-04/06 1. 2. 3. 4. 5. 5. 6. Updated “Features” on page 1.
4. 5. 6. 7. 8. Updated “Bit Rate Generator Unit” on page 251. Updated “Maximum speed vs. VCC” on page 377. Updated “Ordering Information” on page 424. Updated “Packaging Information” on page 429. Package 64M1 replaced by 64M2. Updated “Errata” on page 433. 1. 2. 3. 4. JTAG ID/Signature for ATmega640 updated: 0x9608. Updated Table 43 on page 94. Updated “Serial Programming Instruction set” on page 359. Updated “Errata” on page 433. 1. Initial version. Rev. 2549B-05/05 Rev.
ATmega640/1280/1281/2560/2561 Table of Contents Features................................................................................................ 1 Pin Configurations............................................................................... 2 Disclaimer ............................................................................................................. 4 Overview............................................................................................... 5 Block Diagram ............
Power Management and Sleep Modes............................................. 50 Sleep Modes....................................................................................................... Idle Mode ............................................................................................................ ADC Noise Reduction Mode............................................................................... Power-down Mode..............................................................................
ATmega640/1280/1281/2560/2561 Timer/Counter Clock Sources........................................................................... Counter Unit...................................................................................................... Input Capture Unit............................................................................................. Output Compare Units ...................................................................................... Compare Match Output Unit ..................
Overview........................................................................................................... USART MSPIM vs. SPI .................................................................................... Clock Generation .............................................................................................. SPI Data Modes and Timing............................................................................. Frame Formats ..............................................................
ATmega640/1280/1281/2560/2561 Data Registers .................................................................................................. Boundary-scan Specific JTAG Instructions ...................................................... Boundary-scan Chain ....................................................................................... Boundary-scan Related Register in I/O Memory .............................................. ATmega640/1280/1281/2560/2561 Boundary-scan Order.......................
Standby Supply Current.................................................................................... Pin Pull-up ........................................................................................................ Pin Driver Strength ........................................................................................... Pin Threshold and Hysteresis........................................................................... BOD Threshold and Analog Comparator Offset .............................
ATmega640/1280/1281/2560/2561 Rev. 2549H-06/06............................................................................................. Rev. 2549G-06/06 ............................................................................................ Rev. 2549F-04/06 ............................................................................................. Rev. 2549E-04/06............................................................................................. Rev. 2549D-12/05.........................
viii ATmega640/1280/1281/2560/2561 2549K–AVR–01/07
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