Datasheet

81
7799D–AVR–11/10
ATmega8U2/16U2/32U2
Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure.
Table 12-10. Overriding Signals for Alternate Functions PD7..PD4
Signal Name
PD7/T0/INT7/
HBW/CTS
PD6/INT6/
RTS PD5/XCK/PCINT12 PD4/INT5
PUOE CTS RTS 0 0
PUOV
PORTD7 •
PUD
00 0
DDOE CTS RTS 0 0
DDOV 0 1 0 0
PVOE 0
RTS
OUTPUT
ENABLE
XCK OUTPUT ENABLE 0
PVOV 0
RTS
OUTPUT
XCK1 OUTPUT 0
DIEOE
INT7/
CTS
ENABLE
INT6
ENABLE
PCINT12 ENABLE
INT5
ENABLE
DIEOV 1 1 1 1
DI
T0 INPUT
INT7 INPUT
CTS INPUT
INT6 INPUT
XCK INPUT
PCINT12 INPUT
INT5 INPUT
AIO – – – –
Table 12-11. Overriding Signals for Alternate Functions in PD3..PD0
(1)
Signal Name PD3/INT3/TXD1
PD2/INT2/RXD1/
AIN1 PD1/INT1/AIN0 PD0/INT0/OC0B
PUOE TXEN1 RXEN1 0 0
PUOV 0 PORTD2 •
PUD 0 0
DDOE TXEN1 RXEN1 0 0
DDOV 1 0 0 0
PVOE TXEN1 0 0 OC0B ENABLE
PVOV TXD1 0 0 OC0B
DIEOE INT3 ENABLE
INT2 ENABLE
AIN1 ENABLE
INT1 ENABLE
AIN0 ENABLE
INT0 ENABLE
DIEOV 1 AIN1 ENABLE AIN0 ENABLE 1
DI INT3 INPUT INT2 INPUT/RXD1 INT1 INPUT INT0 INPUT
AIO – AIN1 INPUT AIN0 INPUT –