Datasheet

58
7799D–AVR–11/10
ATmega8U2/16U2/32U2
• Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag
This bit is set when a first time-out occurs in the Watchdog Timer and if the WDEWIE bit is
enabled. WDEWIF is automatically cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF can be cleared by writing a logic one to the flag.
When the I-bit in SREG and WDEWIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 2 - WDEWIE: Watchdog Early Warning Interrupt Enable
When this bit has been set by software, an interrupt will be generated on the watchdog interrupt
vector when the Early warning flag is set to one by hardware.
• Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider
Table 10-2. Watchdog Timer Clock Divider Configuration
WCLKD2 WCLKD1 WCLKD0 Mode
000
Clk
WDT
= Clk
128k
001Clk
WDT
= Clk
128k
/ 3
010Clk
WDT
= Clk
128k
/ 5
011Clk
WDT
= Clk
128k
/ 7
100Clk
WDT
= Clk
128k
/ 9
101Clk
WDT
= Clk
128k
/ 11
110Clk
WDT
= Clk
128k
/ 13
111Clk
WDT
= Clk
128k
/ 15
Table 10-3. Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1)
WDP3 WDP2 WDP1 WDP0
Number of WDT Oscillator
Cycles before 1st time-out
(Early warning)
Early warning Typical
Time-out at
V
CC
= 5.0V
Watchdog
Reset/Interrupt Typical
Time-out at
V
CC
= 5.0V
0 0 0 0 2K (2048) cycles 16 ms 32 ms
0 0 0 1 4K (4096) cycles 32 ms 64 ms
0 0 1 0 8K (8192) cycles 64 ms 128 ms
0 0 1 1 16K (16384) cycles 0.125 s 0.250 s
0 1 0 0 32K (32768) cycles 0.25 s 0.5 s
0 1 0 1 64K (65536) cycles 0.5 s 1.0 s
0 1 1 0 128K (131072) cycles 1.0 s 2.0 s
0 1 1 1 256K (262144) cycles 2.0 s 4.0 s
1 0 0 0 512K (524288) cycles 4.0 s 8.0 s
1 0 0 1 1024K (1048576) cycles 8.0 s 16.0 s