Datasheet

270
7799D–AVR–11/10
ATmega8U2/16U2/32U2
Table 26-7. SPI Interface Timing Requirements (Slave Mode)
26.8 Hardware Boot EntranceTiming Characteristics
Figure 26-4. Hardware Boot Timing Requirements
26.9 Parallel Programming Characteristics
Figure 26-5. Parallel Programming Timing, Including some General Timing Requirements
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
Table 26-8. Hardware Boot Timings
Symbol Parameter
Min Max
tSHRH
HWB low Setup before Reset High 0
tHHRH
HWB low Hold after Reset High
StartUpTime(SUT) +
Time Out Delay(TOUT)
RESET
ALE/HWB
t
SHRH
t
HHRH
Data & Contol
(DATA, XA0/1, BS1, BS2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL