Datasheet

225
7799D–AVR–11/10
ATmega8U2/16U2/32U2
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
22.2.2 ACMUX – Analog Comparator Input Multiplexer
• Bit 2, 0 – CMUX2:0: Analog Comparator Selection Bits
The value of these bits selects which combination of analog inputs are connected to the analog
comparator.
The different settings are shown in Table 22-2.
22.2.3 DIDR1 – Digital Input Disable Register 1
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AINx pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
Table 22-1. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle.
0 1 Reserved
1 0 Comparator Interrupt on Falling Output Edge.
1 1 Comparator Interrupt on Rising Output Edge.
Bit 76543210
(0x7D)
– – – – – CMUX2 CMUX1 CMUX0 ACMUX
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 22-2. CMUX2:0 Settings
CMUX2 CMUX1 CMUX0 Comparator Input
0 0 0 AIN1
0 0 1 AIN2
0 1 0 AIN3
0 1 1 AIN4
1 0 0 AIN5
1 0 1 AIN6
1 1 0 Reserved
1 1 1 Reserved
Bit 76543210
– AIN6D AIN5D AIN4D AIN3D AIN2D AIN1D AIN0D DIDR1
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0