Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 125 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz • Non-volatile Program and Data Memories – 8K/16K/32K Bytes of In-System Self-Programmable Flash – 512/512/1024 EEPROM – 512/512/1024 Internal SRAM – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85C/ 100 years at
ATmega8U2/16U2/32U2 1. Pin Configurations PC5 ( PCINT9/ OC.1B) UGND UCAP PC4 (PCINT10) D+ Pinout AVCC UVCC D- Figure 1-1. 32 31 30 29 28 27 26 25 (AIN0 / INT1) PD1 (RXD1 / AIN1 / INT2) PD2 24 23 22 21 20 19 18 17 QFN32 Reset (PC1 / dW) PC6 (OC.1A / PCINT8) PC7 (INT4 / ICP1 / CLKO) PB7 (PCINT7 / OC.0A / OC.
ATmega8U2/16U2/32U2 2. Overview The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram PD7 - PD0 PORTC DRIVERS ANALOG COMPARATOR + - PORTD DRIVERS DATA REGISTER PORTD PB7 - PB0 PC7 - PC0 DATA DIR. REG.
ATmega8U2/16U2/32U2 architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega8U2/16U2/32U2 2.2.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega8U2/16U2/32U2 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
ATmega8U2/16U2/32U2 6. AVR CPU Core 6.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 Architectural Overview Figure 6-1.
ATmega8U2/16U2/32U2 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATmega8U2/16U2/32U2 conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 6.4.
ATmega8U2/16U2/32U2 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 6.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega8U2/16U2/32U2 Figure 6-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH 7 YL 0 R29 (0x1D) Z-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 6.
ATmega8U2/16U2/32U2 6.6.1 SPH and SPL – Stack Pointer High and Low Register Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Read/Write Initial Value 6.
ATmega8U2/16U2/32U2 6.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
ATmega8U2/16U2/32U2 CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..
ATmega8U2/16U2/32U2 Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 6.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum.
ATmega8U2/16U2/32U2 7. AVR Memories This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 7.1 In-System Reprogrammable Flash Program Memory The ATmega8U2/16U2/32U2 contains 8K/16K/32K bytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega8U2/16U2/32U2 Figure 7-1. Program Memory Map Program Memory 0x00000 Application Flash Section Boot Flash Section 0x7FFF (32KBytes) 0x3FFF (16KBytes) 0x1FFF (8KBytes) 7.2 SRAM Data Memory Figure 7-2 shows how the ATmega8U2/16U2/32U2 SRAM Memory is organized. The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
ATmega8U2/16U2/32U2 The 32 general purpose working registers, 64 I/O registers, and the 512/512/1024bytes of internal data SRAM in the ATmega8U2/16U2/32U2 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 7-2. Data Memory Map Data Memory 32 Registers 64 I/O Registers 160 Ext I/O Reg. $0000 - $001F $0020 - $005F $0060 - $00FF $0100 Internal SRAM (512/512/1024 x 8) $2FF/$2FF/$4FF (8U2/16U2/32U2) 7.2.
ATmega8U2/16U2/32U2 For a detailed description of SPI, debugWIRE and Parallel data downloading to the EEPROM, see page 259, page 244, and page 250 respectively. 7.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function, however, lets the user software detect when the next byte can be written.
ATmega8U2/16U2/32U2 Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them.
ATmega8U2/16U2/32U2 7.5.3 EECR – The EEPROM Control Register Bit 7 6 5 4 3 2 1 0 0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 EECR • Bits 7:6 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE.
ATmega8U2/16U2/32U2 1. Wait until EEPE becomes zero. 2. Wait until SELFPRGEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 6. Within four clock cycles after setting EEMPE, write a logical one to EEPE. The EEPROM can not be programmed during a CPU write to the Flash memory.
ATmega8U2/16U2/32U2 Assembly Code Example(1) EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega8U2/16U2/32U2 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega8U2/16U2/32U2 7.5.
ATmega8U2/16U2/32U2 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 42. The clock systems are detailed below. Figure 8-1.
ATmega8U2/16U2/32U2 8.1.4 8.2 USB Clock – clkUSB The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL running at 48 MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock register should be programmed by software to generate a 8 MHz clock on the PLL input. Clock Switch In the ATmega8U2/16U2/32U2 product, the Clock Multiplexer and the System Clock Prescaler can be modified by software. 8.2.
ATmega8U2/16U2/32U2 Figure 8-3. Example of clock switching with wake-up from Device upstream-resume 2 Upstream Resume from device USB non-Idle Idle Ext CPU Clock non-Idle (Suspend) RC 2 Ext External Oscillator RC oscillator 3ms 8.2.2 8.2.2.1 Watchdog wake-up from power-down Clock switch Algorythm Swith from external clock to RC clock if (Usb_suspend_detected()) // if (UDINT.SUSPI == 1) { Usb_ack_suspend(); // UDINT.SUSPI = 0; Usb_freeze_clock(); // USBCON.
ATmega8U2/16U2/32U2 8.3 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Device Clocking Options Select(1) Table 8-1.
ATmega8U2/16U2/32U2 The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
ATmega8U2/16U2/32U2 3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 8-4. Table 8-4.
ATmega8U2/16U2/32U2 8.5 Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-4. Either a quartz crystal or a ceramic resonator may be used. This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving other clock inputs and in noisy environments.
ATmega8U2/16U2/32U2 Table 1. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Oscillator Source / Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 (1) 0 00 Ceramic resonator, fast rising power 258 CK 14CK + 4.1 ms Ceramic resonator, slowly rising power 258 CK 14CK + 65 ms(1) 0 01 Ceramic resonator, BOD enabled 1K CK 14CK(2) 0 10 Ceramic resonator, fast rising power 1K CK 14CK + 4.
ATmega8U2/16U2/32U2 Notes: 1. The device is shipped with this option selected. 2. The frequency ranges are preliminary values. Actual values are TBD. 3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-5 on page 31. Table 8-7.
ATmega8U2/16U2/32U2 8.7 External Clock The device can utilize a external clock source as shown in Figure 8-5. To run the device on an external clock, the CKSEL Fuses must be programmed as shown in Table 8-1. Figure 8-5. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 8-8. Table 8-8.
ATmega8U2/16U2/32U2 decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkCPU, and clkFLASH are divided by a factor as shown in Table 8-9 on page 40. When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system.
ATmega8U2/16U2/32U2 Figure 8-6. PLL Clocking System PLOCK PLLE PLLITM PINDIV CKSEL3:0 /48 XTAL1 XTAL2 1 TclkTimer1 Lock Detector T1 0 /2 1 XTAL OSCILLATOR PLL clock Prescaler RC OSCILLATOR 8 MHz PLL clk 8MHz clk USB 0 To System Clock Prescaler PDIV3..0 PLLUSB 8.11 8.11.
ATmega8U2/16U2/32U2 lator is selected by the fuse bits configuration. The firmware has to check if the clock is correctly started before selected it. 8.11.2 CLKSEL1 – Clock Selection Register 1 Bit 7 6 5 4 3 2 1 0 RCCKSE L3 RCCKSE L2 RCCKSE L1 RCCKSE L0 EXCKSE L3 EXCKSE L2 EXCKSE L1 EXCKSE L0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 1 0 0 0 0 0 (0xD1) CLKSEL1 • Bit 7:4 – RCCKSEL[3:0]: CKSEL for RC oscillator Clock configuration for the RC Oscillator.
ATmega8U2/16U2/32U2 the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 261 on page 266. Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7 bit determines the range of operation for the oscillator.
ATmega8U2/16U2/32U2 Table 8-9. 8.11.
ATmega8U2/16U2/32U2 • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started. Note that the Calibrated 8 MHz Internal RC oscillator is automatically enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) is set. The PLL must be disabled before entering Power down mode in order to stop Internal RC Oscillator and avoid extra-consumption. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock.
ATmega8U2/16U2/32U2 9. Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 9.2 Sleep Modes Figure 8-1 on page 26 presents the different clock systems in the ATmega8U2/16U2/32U2, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
ATmega8U2/16U2/32U2 Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow, USART Transmit Complete or some USB interrupts (like SOFI, WAKEUPI...).
ATmega8U2/16U2/32U2 when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. 9.
ATmega8U2/16U2/32U2 enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1).
ATmega8U2/16U2/32U2 9.10.2 PRR0 – Power Reduction Register 0 Bit 7 6 5 4 3 2 1 (0x64) - - PRTIM0 – PRTIM1 PRSPI - 0 - Read/Write R/W R/W R/W R R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 PRR0 • Bit 7:6 - Res: Reserved bits These bits are reserved and will always read as zero. • Bit 5 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module.
ATmega8U2/16U2/32U2 10. System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega8U2/16U2/32U2 Figure 10-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF USBRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER USB Device Reset Detection Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 267.
ATmega8U2/16U2/32U2 Figure 10-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 267) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATmega8U2/16U2/32U2 10.2.3 Brown-out Detection ATmega8U2/16U2/32U2 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
ATmega8U2/16U2/32U2 that remains enabled. This allows the device to stay attached to the bus during and after the reset, while enhancing firmware reliability. Figure 10-7. USB Reset During Operation (USB Lines) CC 10.3 t USBRSTMIN End of Reset DP USB Traffic USB Traffic DM Internal Voltage Reference ATmega8U2/16U2/32U2 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator. 10.3.
ATmega8U2/16U2/32U2 when the counter reaches a given time-out value. The WDT gives an interrupt or a system reset when the counter reaches two times the given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued. WCLKD0 WCLKD1 Figure 10-8.
ATmega8U2/16U2/32U2 While the WDT prescaler allows only even division factors (2, 4, 8...), the WDT peripheral also includes a clock divider that directly acts on the clock source. This divider handles odd division factors (3, 5, 7). In combination with the prescaler, a large number of time-out values can be obtained.
ATmega8U2/16U2/32U2 Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
ATmega8U2/16U2/32U2 Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<
ATmega8U2/16U2/32U2 • Bit 5 – USBRF: USB Reset Flag This bit is set if a USB Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 4 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs.
ATmega8U2/16U2/32U2 function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. Table 10-1.
ATmega8U2/16U2/32U2 • Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag This bit is set when a first time-out occurs in the Watchdog Timer and if the WDEWIE bit is enabled. WDEWIF is automatically cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF can be cleared by writing a logic one to the flag. When the I-bit in SREG and WDEWIE are set, the Watchdog Time-out Interrupt is executed.
ATmega8U2/16U2/32U2 Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1) (Continued) Table 10-3. WDP3 WDP2 WDP1 WDP0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Number of WDT Oscillator Cycles before 1st time-out (Early warning) Early warning Typical Time-out at VCC = 5.0V Watchdog Reset/Interrupt Typical Time-out at VCC = 5.0V Reserved Watchdog Timer Prescale Select, DIV = 1 (CLKwdt = CLK128 / 3) Table 10-4. Early warning Typical Time-out at VCC = 5.
ATmega8U2/16U2/32U2 Watchdog Timer Prescale Select, DIV = 2 (CLKwdt = CLK128 / 5) Table 10-5. Early warning Typical Time-out at VCC = 5.0V Watchdog Reset/Interrupt Typical Time-out at VCC = 5.0V WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles before 1st time-out (Early warning) 0 0 0 0 2K (2048) cycles 80 ms 160 ms 0 0 0 1 4K (4096) cycles 160 ms 320 ms 0 0 1 0 8K (8192) cycles 320 ms 640 ms 0 0 1 1 16K (16384) cycles 0.625 s 1.
ATmega8U2/16U2/32U2 Watchdog Timer Prescale Select, DIV = 3 (CLKwdt = CLK128 / 7) (Continued) Table 10-6. WDP3 WDP2 WDP1 WDP0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Number of WDT Oscillator Cycles before 1st time-out (Early warning) Early warning Typical Time-out at VCC = 5.0V Watchdog Reset/Interrupt Typical Time-out at VCC = 5.0V Reserved Watchdog Timer Prescale Select, DIV = 4 (CLKwdt = CLK128 / 9) Table 10-7. Early warning Typical Time-out at VCC = 5.
ATmega8U2/16U2/32U2 Watchdog Timer Prescale Select, DIV = 5 (CLKwdt = CLK128 / 11) Table 10-8. Early warning Typical Time-out at VCC = 5.0V Watchdog Reset/Interrupt Typical Time-out at VCC = 5.0V WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles before 1st time-out (Early warning) 0 0 0 0 2K (2048) cycles 88 ms 176 ms 0 0 0 1 4K (4096) cycles 176 ms 352 ms 0 0 1 0 8K (8192) cycles 352 ms 704 ms 0 0 1 1 16K (16384) cycles 704 ms 1.4 s 0 1 0 0 32K (32768) cycles 1.
ATmega8U2/16U2/32U2 Watchdog Timer Prescale Select, DIV = 6(CLKwdt = CLK128 / 13) (Continued) Table 10-9. WDP3 WDP2 WDP1 WDP0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Number of WDT Oscillator Cycles before 1st time-out (Early warning) Early warning Typical Time-out at VCC = 5.0V Watchdog Reset/Interrupt Typical Time-out at VCC = 5.0V Reserved Table 10-10. Watchdog Timer Prescale Select, DIV = 7 (CLKwdt = CLK128 / 15) Early warning Typical Time-out at VCC = 5.
ATmega8U2/16U2/32U2 11. Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega8U2/16U2/32U2. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. 11.2 Interrupt Vectors in ATmega8U2/16U2/32U2 Table 11-1. Reset and Interrupt Vectors Vector No.
ATmega8U2/16U2/32U2 Reset and Interrupt Vectors (Continued) Table 11-1. Vector No. Program Address(2) 27 Source Interrupt Definition $0034 ANALOG COMP Analog Comparator 28 $0036 EE READY EEPROM Ready 29 $0038 SPM READY Store Program Memory Ready Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Memory Programming” on page 246. 2.
ATmega8U2/16U2/32U2 a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles.
ATmega8U2/16U2/32U2 12. I/O-Ports 12.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega8U2/16U2/32U2 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 12-2.
ATmega8U2/16U2/32U2 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 12.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 12.2.
ATmega8U2/16U2/32U2 Figure 12-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega8U2/16U2/32U2 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ATmega8U2/16U2/32U2 12.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega8U2/16U2/32U2 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 12-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 12-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 12-2.
ATmega8U2/16U2/32U2 12.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 12-3. Table 12-3.
ATmega8U2/16U2/32U2 • PDI/MOSI/PCINT2 – Port B, Bit 2 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the AT90USB82/162. MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2.
ATmega8U2/16U2/32U2 .Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals shown in Figure 12-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.. Overriding Signals for Alternate Functions in PB7..PB4 Table 12-4.
ATmega8U2/16U2/32U2 12.3.2 Alternate Functions of Port C The Port C alternate function is as follows: Table 12-6. Port C Pins Alternate Functions Port Pin Alternate Function PC7 ICP1/INT4/CLKO PC6 PCINT8/OC1A PC5 PCINT9/OC1B PC4 PCINT10 - - PC2 PCINT11 PC1 Reset, dW PC0 XTAL2 The alternate pin configuration is as follows: • ICP1/INT4/CLK0, Bit 7 ICP1, Input Capture pin 1 :The PC7 pin can act as an input capture for Timer/Counter1.
ATmega8U2/16U2/32U2 Reset, Reset input. External Reset input is active low and enabled by unprogramming ("1") the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. dW, debugWire channel. When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated.
ATmega8U2/16U2/32U2 12.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 12-9. Table 12-9.
ATmega8U2/16U2/32U2 TXD1, USART1 Transmit Data : When the USART1 Transmitter is enabled, this pin is configured as an ouput regardless of DDRD3. • INT2/AIN1/RXD1, Bit 2 INT2, External Interrupt source 2: The PD2 pin can serve as an external interrupt source to the MCU. AIN1, Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. RXD1, USART1 Receive Data : When the USART1 Receiver is enabled, this pin is configured as an input regardless of DDRD2.
ATmega8U2/16U2/32U2 Table 12-10. Overriding Signals for Alternate Functions PD7..
ATmega8U2/16U2/32U2 12.4 12.4.1 Register Description for I/O-Ports MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATmega8U2/16U2/32U2 12.4.8 PORTD – Port D Data Register Bit 12.4.9 7 6 5 4 3 2 1 0 0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRD – Port D Data Direction Register Bit 12.4.
ATmega8U2/16U2/32U2 13. External Interrupts 13.1 Overview The External Interrupts are triggered by the INT[7:0] pin or any of the PCINT[12:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT[7:0] or PCINT[12:0] pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin toggles. PCMSK0 Register control which pins contribute to the pin change interrupts.
ATmega8U2/16U2/32U2 interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. Interrupt Sense Control(1) Table 13-1. ISCn1 ISCn0 0 0 The low level of INTn generates an interrupt request. 0 1 Any edge of INTn generates asynchronously an interrupt request. 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request.
ATmega8U2/16U2/32U2 13.2.3 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x1D (0x3D) INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 7:0 – INT[7:0]: External Interrupt Request 7:0 Enable When an INT[7:0] bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled.
ATmega8U2/16U2/32U2 • Bit 1:0 – PCIF[1:0]: Pin Change Interrupt Flag 1:0 When a logic change on any PCINT[12:8]/[7:0] pin triggers an interrupt request, PCIF1/0 becomes set (one). If the I-bit in SREG and the PCIE1/0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 13.2.
ATmega8U2/16U2/32U2 14. Timer/Counter0 and Timer/Counter1 Prescalers 14.1 Overview Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0 or 1. 14.2 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
ATmega8U2/16U2/32U2 The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
ATmega8U2/16U2/32U2 • Bits 6:1 – Res: Reserved These bits are reserved and will always read as zero. • Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters When this bit is one, Timer/Counter0 and Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0 and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect all timers.
ATmega8U2/16U2/32U2 15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
ATmega8U2/16U2/32U2 uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B).
ATmega8U2/16U2/32U2 count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
ATmega8U2/16U2/32U2 Figure 15-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
ATmega8U2/16U2/32U2 generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
ATmega8U2/16U2/32U2 15.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x[1:0] = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 102. For fast PWM mode, refer to Table 15-3 on page 102, and for phase correct PWM refer to Table 15-4 on page 103.
ATmega8U2/16U2/32U2 Figure 15-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega8U2/16U2/32U2 PWM mode is shown in Figure 15-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 15-6.
ATmega8U2/16U2/32U2 feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 15.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
ATmega8U2/16U2/32U2 one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 15-4 on page 103). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega8U2/16U2/32U2 Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 15-10.
ATmega8U2/16U2/32U2 15.9 15.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
ATmega8U2/16U2/32U2 Table 15-4 shows the COM0A1:0 bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 15-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
ATmega8U2/16U2/32U2 Table 15-4 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 15-7. COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
ATmega8U2/16U2/32U2 15.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATmega8U2/16U2/32U2 Clock Select Bit Description (Continued) Table 15-9. CS02 CS01 CS00 Description 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output.
ATmega8U2/16U2/32U2 • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
ATmega8U2/16U2/32U2 16. 16-bit Timer/Counter 1 with PWM 16.1 Features • • • • • • • • • • • 16.2 True 16-bit Design (i.e.
ATmega8U2/16U2/32U2 Figure 16-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic TCLK Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform Generation = OCnA OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation DATABUS = OCnB OCRnB OCFnC (Int.Req.) Waveform Generation = OCnC OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.
ATmega8U2/16U2/32U2 See “Output Compare Units” on page 117.. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See “Analog Comparator” on page 223.
ATmega8U2/16U2/32U2 Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. See “Code Examples” on page 6. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
ATmega8U2/16U2/32U2 Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i
ATmega8U2/16U2/32U2 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega8U2/16U2/32U2 16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega8U2/16U2/32U2 The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
ATmega8U2/16U2/32U2 Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value.
ATmega8U2/16U2/32U2 Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location).
ATmega8U2/16U2/32U2 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega8U2/16U2/32U2 16.8 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega8U2/16U2/32U2 non-PWM modes refer to Table 16-1 on page 130. For fast PWM mode refer to Table 16-2 on page 130, and for phase correct and phase and frequency correct PWM refer to Table 16-3 on page 131. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 16.9 Modes of Operation The mode of operation, i.e.
ATmega8U2/16U2/32U2 Figure 16-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega8U2/16U2/32U2 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
ATmega8U2/16U2/32U2 to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values.
ATmega8U2/16U2/32U2 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log TOP + 1 R PCPWM = ----------------------------------log 2 In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn[3:0] = 1, 2, or 3), the value in ICRn (WGMn[3:0] = 10), or the value in OCRnA (WGMn3:0 = 11).
ATmega8U2/16U2/32U2 ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
ATmega8U2/16U2/32U2 the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log TOP + 1 R PFCPWM = ----------------------------------log 2 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn[3:0] = 8), or the value in OCRnA (WGMn[3:0] = 9). The counter has then reached the TOP and changes the count direction.
ATmega8U2/16U2/32U2 Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
ATmega8U2/16U2/32U2 Figure 16-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATmega8U2/16U2/32U2 Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 16.11 Register Description 16.11.
ATmega8U2/16U2/32U2 . Table 16-1. Compare Output Mode, non-PWM COMnA1/COMnB1/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 Toggle OCnA/OCnB/OCnC on compare match. 1 0 Clear OCnA/OCnB/OCnC on compare match (set output to low level). 1 1 Set OCnA/OCnB/OCnC on compare match (set output to high level). Description Table 16-2 shows the COMnx[1:0] bit functionality when the WGMn[3:0] bits are set to the fast PWM mode. Table 16-2.
ATmega8U2/16U2/32U2 Table 16-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COMnA1/COMnB/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 WGM1[3:0] = 8, 9 10 or 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected. 1 0 Clear OCnA/OCnB/OCnC on compare match when up-counting.
ATmega8U2/16U2/32U2 Waveform Generation Mode Bit Description(1) Table 16-4.
ATmega8U2/16U2/32U2 16.11.2 TCCR1B – Timer/Counter1 Control Register B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x81) TCCR1B • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICPn) is filtered.
ATmega8U2/16U2/32U2 If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 16.11.
ATmega8U2/16U2/32U2 16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A Bit 16.11.6 6 5 4 3 OCR1A[15:8] (0x88) OCR1A[7:0] 2 1 0 OCR1AH OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4 3 2 1 0 OCR1BH and OCR1BL – Output Compare Register 1 B Bit 16.11.
ATmega8U2/16U2/32U2 • Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 64.) is executed when the ICFn Flag, located in TIFRn, is set.
ATmega8U2/16U2/32U2 • Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag. OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
ATmega8U2/16U2/32U2 17. SPI – Serial Peripheral Interface 17.1 Features • • • • • • • • 17.
ATmega8U2/16U2/32U2 The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
ATmega8U2/16U2/32U2 Functions” on page 72. Table 17-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See “Alternate Functions of Port B” on page 74 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
ATmega8U2/16U2/32U2 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega8U2/16U2/32U2 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega8U2/16U2/32U2 means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 17.3.
ATmega8U2/16U2/32U2 CPOL Functionality Table 17-2. Leading Edge Trailing Edge SPI Mode CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3 Figure 17-3.
ATmega8U2/16U2/32U2 17.5 17.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
ATmega8U2/16U2/32U2 • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 17-5. 17.5.
ATmega8U2/16U2/32U2 17.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB – – – – – – LSB Read/Write R/W R R R R R R R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
ATmega8U2/16U2/32U2 18. USART 18.1 Features • • • • • • • • • • • • • 18.
ATmega8U2/16U2/32U2 Figure 18-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1. See Figure 1-1 on page 2, Table 12-9 on page 79 and for USART pin placement.
ATmega8U2/16U2/32U2 for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 18-2 shows a block diagram of the clock generation logic. Figure 18-2.
ATmega8U2/16U2/32U2 Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 18-1.
ATmega8U2/16U2/32U2 18.3.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 18-2 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver.
ATmega8U2/16U2/32U2 A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 18-4 illustrates the possible combinations of the frame formats.
ATmega8U2/16U2/32U2 18.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization.
ATmega8U2/16U2/32U2 18.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega8U2/16U2/32U2 a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega8U2/16U2/32U2 UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
ATmega8U2/16U2/32U2 bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
ATmega8U2/16U2/32U2 Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
ATmega8U2/16U2/32U2 18.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
ATmega8U2/16U2/32U2 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 18.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e.
ATmega8U2/16U2/32U2 Figure 18-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
ATmega8U2/16U2/32U2 Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
ATmega8U2/16U2/32U2 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) Table 18-2. D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.
ATmega8U2/16U2/32U2 The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. 18.9.
ATmega8U2/16U2/32U2 stop sending characters. RTS usage and so associated flow control is enabled using RTSEN bit in UCSRnD. Figure 18-8. shows a reception example. Figure 18-8. Reception Flow Control Waveform Example FIFO Index 0 1 2 1 0 1 CPU Read C1 C2 RXD C3 RTS Figure 18-9.
ATmega8U2/16U2/32U2 18.11 Register Description 18.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
ATmega8U2/16U2/32U2 • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
ATmega8U2/16U2/32U2 • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn Flags. • Bit 3 – TXENn: Transmitter Enable n Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled.
ATmega8U2/16U2/32U2 Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 18-5. UPMn Bits Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 18-6.
ATmega8U2/16U2/32U2 18.11.5 UCSRnD – USART Control and Status Register n D Bit 7 6 5 4 3 2 1 0 - - - - - - CTSEN RTSEN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 UCSRnD • Bits 1 – CTSEN : USART CTS Enable Set this bit to one by firmware to enable the transmission flow control (CTS). Transmission is allowed if CTS = 0. Set this bit to zero by firmware to disable the transmission flow control (CTS). Transmission is always allowed.
ATmega8U2/16U2/32U2 Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Table 18-9. fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz Baud Rate (bps) UBRR 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.
ATmega8U2/16U2/32U2 Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz Baud Rate (bps) U2Xn = 0 UBRR fosc = 4.0000 MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR fosc = 7.3728 MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR U2Xn = 1 Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.
ATmega8U2/16U2/32U2 Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.
ATmega8U2/16U2/32U2 Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.
ATmega8U2/16U2/32U2 19. USART in SPI Mode 19.1 Features • • • • • • • • 19.
ATmega8U2/16U2/32U2 Table 19-1. Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRRn Value f OSC BAUD = -------------------------------------2 UBRRn + 1 f OSC UBRRn = -------------------–1 2BAUD Synchronous Master mode Note: 19.4 1.
ATmega8U2/16U2/32U2 19.5 Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB first A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly.
ATmega8U2/16U2/32U2 Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
ATmega8U2/16U2/32U2 transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buffer.
ATmega8U2/16U2/32U2 19.6.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 19.6.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. 19.
ATmega8U2/16U2/32U2 19.7.3 UCSRnB – USART MSPIM Control and Status Register n B Bit 7 6 5 4 3 2 1 RXCIEn TXCIEn UDRIE RXENn TXENn – – 0 – Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag.
ATmega8U2/16U2/32U2 19.7.4 UCSRnC – USART MSPIM Control and Status Register n C Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 – – – UDORDn UCPHAn UCPOLn Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC • Bit 7:6 - UMSELn[1:0]: USART Mode Select These bits select the mode of operation of the USART as shown in Table 19-3. See “UCSRnC – USART Control and Status Register n C” on page 169 for full description of the normal USART operation.
ATmega8U2/16U2/32U2 However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only master operation is supported by the USART in MSPIM mode, the following features differ between the two modules: • The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer.
ATmega8U2/16U2/32U2 20. USB Controller 20.1 Features • USB 2.0 Full-speed device • Ping-pong mode (dual bank), with transparent switch • 176 bytes of DPRAM – 1 endpoint of 64 bytes max (default control endpoint) – 2 endpoints of 64 bytes max (one bank) – 2 endpoints of 64 bytes max (one or two banks) 20.2 Overview The USB controller provides the hardware to implement a USB2.0 compliant Full-Speed USB device in the ATmega8U2/16U2/32U2.
ATmega8U2/16U2/32U2 20.3 USB Module Powering Options Depending on the selected target application power supply (VCC), the ATmega8U2/16U2/32U2 USB controller requires different powering schemes, see Figure 20-2 on page 186. Figure 20-2. Operating modes versus frequency and power-supply Max Operating Frequency (MHz) VCC (V) 5.5 16 MHz 4.5 USB compliant, with internal regulator 4.0 3.6 8 MHz USB compliant, without internal regulator 3.0 2.7 USB not operational 2 MHz VCC min 0 20.3.
ATmega8U2/16U2/32U2 Figure 20-4. Typical Bus powered application with 3.3V I/O VCC AVCC UCAP 1µF VBUS UVCC UDM D+ UDP D- UVSS UVSS VSS XTAL1 20.3.2 XTAL2 Self Powered device Figure 20-5. Typical Self powered application with 4.0V to 5.5V I/O. External 3.4V - 5.
ATmega8U2/16U2/32U2 Figure 20-6. Typical Self powered application with 3.0V to 3.6 I/O(1) External 3.0V - 3.6V Power Supply UVCC AVCC VCC UCAP 1µF VBUS VBUS UDP D+ Rs=22 UDM DRs=22 UVSS UID UGND UID XTAL1 Note: XTAL2 GND GND 1. The internal 3.3V regulator is bypassed. Disable the regulator to avoid additional power consumption. See the “REGCR – Regulator Control Register” on page 196 for details.
ATmega8U2/16U2/32U2 20.3.3 Design guidelines The following design guidelines should be met: • Serial resistors on USB Data lines must have 22 Ohms value (+/- 5%). • Traces from the input USB receptacle (or from the cable connection in the case of a tethered device) to the USB microcontroller pads should be as short as possible, and follow differential traces routing rules (same length, as near as possible and avoid vias accumulation).
ATmega8U2/16U2/32U2 When the USB controller is in reset state: • USBE is not set • the USB controller clock is stopped in order to minimize the power consumption (FRZCLK=1) • the USB controller is disabled • USB is in the suspend mode • the Device USB controllers internal state is reset • The DPACC bit and the DPADD10:0 field can be set by software. The DPRAM is not cleared. • The SPDCONF bits can be set by software After setting USBE, the USB Controller enters in the Device state.
ATmega8U2/16U2/32U2 Figure 20-10. USB Endpoint Interrupt vector sources Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 NAKINI UEINTX.6 NAKOUTI UEINTX.4 RXSTPI UEINTX.3 RXOUTI UEINTX.2 FLERRE UEIENX.7 NAKINE UEIENX.6 TXSTPE UEIENX.4 TXOUTE UEIENX.3 EPINT UEINT.X USB Endpoi Interrupt Vec RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
ATmega8U2/16U2/32U2 20.5.3 Freeze clock The firmware has the ability to freeze the clock of USB controller by setting the FRZCLK bit, and thereby reduce the power consumption. When FRZCLK is set, it is still possible to access to the following registers: • USBCON • DPRAM direct access registers (DPADD7:0, UEDATX) • UDCON • UDINT • UDIEN When FRZCLK is set, only the asynchronous interrupt may be triggered: • WAKEUPI 20.
ATmega8U2/16U2/32U2 • Endpoints activation: Endpoint 0 to Endpoint 4 are configured, in the growing order. The memory of each is reserved in the DPRAM. • Endpoint disable: The Endpoint 2 is disabled (EPEN=0), but its memory reservation is internally kept by the controller. • Free its memory: The ALLOC bit is cleared: the Endpoint 3 slides down, but the Endpoint 4 does not slide. • Endpoint activation: The firmware chooses to reconfigure the Endpoint 2, but with a bigger size.
ATmega8U2/16U2/32U2 Suspend detected = USB pad power down SUSPI WAKEUPI Clear Suspend by software Clear Resume by software Resume = USB pad wake-up PAD status Active Power Down Active Moreover, the pad can also be put in the Idle mode if the DETACH bit is set. It come back in the Active mode when the DETACH bit is cleared. 20.8 D+/D- Read/write The level of D+ and D- can be read and written using the UPOE register. The USB controller has to be enabled to write a value.
ATmega8U2/16U2/32U2 • Be sure to have interrupts enabled (WAKEUPE) to exit sleep mode • Put the MCU in sleep mode Resuming the USB interface • Enable PLL • Wait PLL lock • Clear USB suspend clock • Clear Resume information 20.10 Registers Description 20.10.
ATmega8U2/16U2/32U2 buffers. Table 20-2. UPWE[I:0] Bits Settings UPWE1 UPWE0 Mode 0 0 Direct drive is disabled. 0 1 Reserved 1 0 Direct drive of DP/DM (UPDRV[1:0] values) 1 1 Reserved • Bit 5:4 – UPDRV[1:0]: USB direct drive values These bits are relevant only when one of the direct drive modes for USB is enable. When UPWE[1:0] is 1:0 the values of these bits are output to USB. The value written to UPDRV1 is output to D+. The value written to UPDRV0 is output to D-.
ATmega8U2/16U2/32U2 21. USB Device Operating modes 21.1 Overview The USB device controller supports full speed data transfers. In addition to the default control endpoint, it provides four other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: • Endpoint 0: Programmable size FIFO up to 64 bytes, default control endpoint • Endpoint 1 and 2: Programmable size FIFO up to 64 bytes. • Endpoint 3 and 4: Programmable size FIFO up to 64 bytes with ping-pong mode.
ATmega8U2/16U2/32U2 • the Rx and Tx banks are cleared and their internal pointers are restored, • the UEINTX, UESTA0X and UESTA1X are restored to their reset value. The data toggle field remains unchanged. The other registers remain unchanged. The endpoint configuration remains active and the endpoint is still enabled. The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as an answer to the CLEAR_FEATURE USB command. 21.
ATmega8U2/16U2/32U2 Figure 21-2. Endpoint activation flow: As long as the endpoint is not correctly configured (CFGOK cleared), the hardware does not acknowledge the packets sent by the host. CFGOK will not be set if the Endpoint size parameter is bigger than the DPRAM size. A clear of EPEN acts as an endpoint reset (see “Endpoint reset” on page 197 for more details).
ATmega8U2/16U2/32U2 UADD contains the default address 00h after a power-up or an USB reset. ADDEN is cleared by hardware: • after a power-up reset, • when an USB reset is received, • or when the macro is disabled (USBE cleared) When this bit is cleared, the default device address 00h is used. 21.8 Suspend, Wake-up and Resume After the USB line has been inactive for a period of 3 ms (J state), the controller set the SUSPI flag and triggers the corresponding interrupt if enabled.
ATmega8U2/16U2/32U2 21.10 Remote Wake-up The Remote Wake-up (or upstream resume) request is the only operation allowed to be sent by the device on its own initiative. Anyway, to do that, the device should first have received a DEVICE_REMOTE_WAKEUP request from the host. • First, the USB controller must have detected the “suspend” state of the line: the remote wake-up can only be sent if the SUSPI bit is set. • The firmware has then the ability to set RMWKUP to send the “upstream resume” stream.
ATmega8U2/16U2/32U2 21.11.2 STALL handshake and Retry mechanism The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the STALLRQ request bit is set and if there is no retry required. 21.12 CONTROL endpoint management A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI interrupt is triggered (if enabled). The RXOUTI interrupt is not triggered. The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints.
ATmega8U2/16U2/32U2 21.12.2 Control Read The next figure shows a control read transaction. The USB controller has to manage the simultaneous write requests from the CPU and the USB host: A NAK handshake is always generated at the first status stage command. When the controller detect the status stage, all the data written by the CPU are erased, and clearing TXINI has no effects. The firmware checks if the transmission is complete or if the reception is complete. The OUT retry is always ACK'ed.
ATmega8U2/16U2/32U2 21.13.1.1 “Manual” mode Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the current bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will switch to the next bank.
ATmega8U2/16U2/32U2 • The CPU can free the bank by clearing FIFOCON when all the data is read, that is: • after “N” read of UEDATX, • as soon as RWAL is cleared by hardware. If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already ready and RXOUTI is set immediately. 21.14 IN endpoint management IN packets are sent by the USB device controller, upon an IN request from the host.
ATmega8U2/16U2/32U2 The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can write data to the bank, and cleared by hardware when the bank is full. 21.14.2 Detailed description The data are written by the CPU, following the next flow: • When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set) and TXINI is set.
ATmega8U2/16U2/32U2 • In a control transaction: ZLP data OUT received during a IN stage, • In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN stage on the IN endpoint The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to perform the following operations: Table 21-1. Abort flow 21.15 Isochronous mode 21.15.1 Underflow An underflow can occur during IN stage if the host attempts to read a bank which is empty.
ATmega8U2/16U2/32U2 It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should write only if the bank is ready to access data (TXINI=1 or RWAL=1). 21.17 Interrupts The next figure shows all the interrupts sources: Figure 21-4. USB Device Controller Interrupt System UPRSMI UDINT.6 EORSMI UDINT.5 UPRSME UDIEN.6 EORSME UDIEN.5 WAKEUPI UDINT.4 WAKEUPE UDIEN.4 EORSTI UDINT.3 SOFI UDINT.2 SUSPI UDINT.0 USB Device Interrupt EORSTE UDIEN.3 SOFE UDIEN.
ATmega8U2/16U2/32U2 Figure 21-5. USB Device Controller Endpoint Interrupt System Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 FLERRE UEIENX.7 NAKINI UEINTX.6 NAKINE UEIENX.6 NAKOUTI UEINTX.4 TXSTPE UEIENX.4 RXSTPI UEINTX.3 Endpoint Interrupt EPINT UEINT.X TXOUTE UEIENX.3 RXOUTI UEINTX.2 RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
ATmega8U2/16U2/32U2 • Bits 7:3 – Res: Reserved These bits are reserved and will always read as zero. • Bit 2 – RSTCPU: USB Reset CPU Bit Writing this bit to one allows the CPU controller to reset the CPU when a USB bus reset condition is detected. When this mode is activated, the next USB bus reset event allows to reset the CPU and all peripherals except the USB controller. This mode allows to perform a software reset, but keep the USB device attached to the bus.
ATmega8U2/16U2/32U2 • Bit 4 – WAKEUPI: Wake-up CPU Interrupt Flag This flag is set by hardware when the USB controller detects a non-idle signal from the USB lines. This WAKEUPI flag can generate a “USB general interrupt” if WAKEUPE bit is set. Writing this bit to zero acknowledges the interrupt source. Writing this bit to one has no effect.Shall be cleared by software. Setting by software has no effect. See “Suspend, Wake-up and Resume” on page 200 for more details.
ATmega8U2/16U2/32U2 • Bit 5 – EORSME: End Of Resume Interrupt Enable Bit Writing this bit to one enables interrupt on EORSMI flag. An end of resume Upstream resume interrupt will be generated only if the EORSME bit is set to one, the Global Interrupt Flag in SREG is written to one, and the EORSMI bit is set. • Bit 4 – WAKEUPE: Wake-up CPU Interrupt Enable Bit Writing this bit to one enables interrupt on WAKEUPI flag.
ATmega8U2/16U2/32U2 21.18.5 UDFNUMH – USB Device Frame Number High Register Bit 7 6 5 4 3 (0xE5) - - - - - 2 1 0 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 FNUM[10:8] UDFNUMH • Bits 7:3 – Res: Reserved These bits are reserved and will always read as zero. • Bits 2:0 – FNUM[10:8]: Frame Number Upper Flag These bits are read-only and updated by the hardware USB controller. These bits contains the 3 MSB of the 11-bits Frame Number information.
ATmega8U2/16U2/32U2 21.18.8 UENUM – USB Endpoint Number Register Bit 7 6 5 4 3 (0xE9) - - - - - 2 1 0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EPNUM[2:0] UENUM • Bits 7:3 – Res: Reserved These bits are reserved and will always read as zero. • Bits 2:0 – EPNUM[2:0] Endpoint Number Bits Writing these bits allows to select the hardware endpoint number that can be accessed by the CPU interface.
ATmega8U2/16U2/32U2 • Bit 4 – STALLRQC: STALL Request Clear Handshake Bit Writing this bit to one disables the pending STALL handshake mechanism triggered by STALLRQ bit. This bit can not be write to zero, it is cleared by hardware immediately after the write to one operation. See “STALL request” on page 201 for more details. • Bit 3 – RSTDT: Reset Data Toggle Bit Writing this bit to one allows to reset the data toggle bit field for the selected endpoint.
ATmega8U2/16U2/32U2 21.18.12 UECFG1X – USB Endpoint Configuration 1 Register Bit 7 (0xED) - 6 5 4 3 Read/Write R R/W R/W R/W R/W Initial Value 0 0 0 0 0 EPSIZE[2:0] 2 EPBK1:0 1 0 ALLOC - R/W R/W R 0 0 0 UECFG1X • Bit 7 – Res: Reserved This bit is reserved and will always read as zero. • Bit 6:4 – EPSIZE[2:0]: Endpoint Size Bits These bits configure the endpoint size for the selected endpoint as shown in Table 21-3. Table 21-3.
ATmega8U2/16U2/32U2 21.18.13 UESTA0X – USB Endpoint Status 0 Register Bit 7 6 5 4 CFGOK OVERFI UNDERFI - Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 (0xEE) 3 2 DTSEQ1:0 1 0 NBUSYBK1:0 UESTA0X • Bit 7 – CFGOK: Configuration Status Flag This flag bit is set by hardware when the selected endpoint size parameter (EPSIZE) and number of banks (EPBK) are correct compared to the max FIFO capacity.
ATmega8U2/16U2/32U2 • Bit 1:0 – NBUSYBK[1:0]: Busy Bank Flag These flags are set by hardware to indicate the number of busy bank for the selected endpoint as shown in Table 21-6. For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer. For OUT endpoint, it indicates the number of busy bank(s) filled by OUT transaction from the host. NBUSYBK[1:0] Bits Settings Table 21-6.
ATmega8U2/16U2/32U2 21.18.15 UEINTX – USB Endpoint Interrupt Register Bit 7 6 5 4 3 2 1 0 FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xE8) UEINTX • Bit 7 – FIFOCON: FIFO Control Bit This bit can only be written to zero by software. Writing this bit to one has no effect. The behavior of this bit depends on the direction of the selected endpoint.
ATmega8U2/16U2/32U2 This flag is set by the USB controller when the current bank contains a new packet. This RXOUTI flag can generate a “USB endpoint interrupt” if RXOUTE bit is set. Writing this bit to zero acknowledges the interrupt source (USB clocks must be enabled before). Writing this bit to one has no effect for an OUT endpoint. • Endpoint IN direction (KILLBK bit) Writing this bit to one kills the last loaded bank. This sequence can be used to cancelled a previously loaded endpoint.
ATmega8U2/16U2/32U2 • Bit 3 – RXSTPE: Received SETUP Interrupt Enable Flag Writing this bit to one enables interrupt on RXSTPI flag. A receiveD setup interrupt will be generated only if the RXSTPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the RXSTPI is set. • Bit 2 – RXOUTE: Received OUT Data Interrupt Enable Flag Writing this bit to one enables interrupt on RXOUTI flag.
ATmega8U2/16U2/32U2 This register contains the number of received byte into the current bank of the selected endpoint. The content of this register is decremented after each write access to the endpoint data register. 21.18.19 UEINT – USB Endpoint Number interrupt Register Bit 7 6 5 (0xF4) - - - 4 3 Read/Write R R R R R Initial Value 0 0 0 0 0 2 1 0 R R R 0 0 0 EPINT4:0 UEINT R • Bits 7:5 – Res: Reserved The value read from these bits is always 0. Do not set these bits.
ATmega8U2/16U2/32U2 22. Analog Comparator 22.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega8U2/16U2/32U2 22.2 22.2.1 Register Description ACSR – Analog Comparator Control and Status Register Bit 7 6 5 4 3 2 1 0 0x30 (0x50) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSR • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator.
ATmega8U2/16U2/32U2 Table 22-1. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 22.2.
ATmega8U2/16U2/32U2 23. Boot Loader Support – Read-While-Write Self-Programming 23.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 23.2 1. A page is a section in the Flash consisting of several bytes (see Table 25-7 on page 249) used during programming.
ATmega8U2/16U2/32U2 23.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega8U2/16U2/32U2 Figure 23-1. Read-While-Write vs.
ATmega8U2/16U2/32U2 Figure 23-2.
ATmega8U2/16U2/32U2 Table 23-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
ATmega8U2/16U2/32U2 is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 23-4. BOOTRST Note: 23.6.3 Boot Reset Fuse(1) Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see Table 23-8 on page 239) 1.
ATmega8U2/16U2/32U2 Figure 23-3. Boot Process Description RESET tSHRH tHHRH PD7/HWB HWBE Ext. Hardware Conditions BOOTRST Reset Vector = Application Reset 23.7 Reset Vector =Boot Lhoader Reset Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file. The number of bits actually used is implementation dependent.
ATmega8U2/16U2/32U2 Figure 23-4. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 23.8 1. The different variables used in Figure 23-4 are listed in Table 23-10 on page 239. Self-Programming the Flash The program memory is updated in a page by page fashion.
ATmega8U2/16U2/32U2 23.8.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
ATmega8U2/16U2/32U2 page 237 for an example. 23.8.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega8U2/16U2/32U2 shown below. Refer to Table 25-4 on page 248 for detailed description and mapping of the Fuse High byte. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.
ATmega8U2/16U2/32U2 Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level.
ATmega8U2/16U2/32U2 call adiw sbiw brne Do_spm ZH:ZL, 2 loophi:looplo, 2 Wrloop ;use subi for PAGESIZEB<=256 ; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<
ATmega8U2/16U2/32U2 23.8.14 ATmega8U2 Boot Loader Parameters In Table 23-8 through Table 23-10, the parameters used in the description of the Self-Programming are given.
ATmega8U2/16U2/32U2 23.8.15 ATmega16U2 Boot Loader Parameters In Table 23-11 through Table 23-13, the parameters used in the description of the Self-Programming are given.
ATmega8U2/16U2/32U2 23.8.16 ATmega32U2 Boot Loader Parameters In Table 23-14 through Table 23-16, the parameters used in the description of the Self-Programming are given.
ATmega8U2/16U2/32U2 23.9 23.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega8U2/16U2/32U2 • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
ATmega8U2/16U2/32U2 24. debugWIRE On-chip Debug System 24.1 Features • • • • • • • • • • 24.
ATmega8U2/16U2/32U2 When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Connecting the RESET pin directly to VCC will not work. • Any capacitors (or additionnal circuitry) connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. Note: 24.4 some releases of JTAG Ice mkII firmware may require a pull-up resistor with a value between 8 and 14 kOhms when operating at 5V.
ATmega8U2/16U2/32U2 25. Memory Programming 25.1 Program And Data Memory Lock Bits The ATmega8U2/16U2/32U2 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 25-1.
ATmega8U2/16U2/32U2 Lock Bit Protection Modes(1)(2) (Continued) Table 25-2. Memory Lock Bits Protection Type BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega8U2/16U2/32U2 Table 25-4. Fuse High Byte Fuse High Byte Bit No Description Default Value : 0xD9 DWEN(4) 7 Enable debugWIRE (and disable Reset capability 1 (unprogrammed, debugWIRE disabled) RSTDSBL 6 Disable Reset (pin can be used as general purpose I/O) 1 (unprogrammed, Reset enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega8U2/16U2/32U2 25.2.1 25.3 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
ATmega8U2/16U2/32U2 25.6 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8U2/16U2/32U2. Pulses are assumed to be at least 250 ns unless otherwise noted. 25.6.1 Signal Names In this section, some pins of the ATmega8U2/16U2/32U2 are referenced by signal names describing their functionality during parallel programming, see Figure 25-1 and Table 25-9.
ATmega8U2/16U2/32U2 Pin Name Mapping Table 25-9. Signal Name in Programming Mode Pin Name I/O PAGEL PD7 I Program Memory and EEPROM data Page Load. BS2 PC6 I Byte Select 2. DATA PB7-0 I/O Function Bi-directional Data bus (Output when OE is low). Table 25-10.
ATmega8U2/16U2/32U2 Table 25-13. Command Byte Bit Encoding Command Byte 25.7 25.7.1 Command Executed 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3.
ATmega8U2/16U2/32U2 6. Wait until RDY/BSY goes high before loading a new command. 25.7.4 Programming the Flash The Flash is organized in pages, see Table 25-7 on page 249. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3.
ATmega8U2/16U2/32U2 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “10”. This selects the address extended high byte. 3. Set DATA = Address extended high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. I. Program Page 1. Set BS2, BS1 to “00” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high (See Figure 25-3 for signal waveforms). J.
ATmega8U2/16U2/32U2 Figure 25-3. Programming the Flash Waveforms(1) F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.H I XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL Note: 25.7.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 25-8 on page 249.
ATmega8U2/16U2/32U2 Figure 25-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 25.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 253 for details on Command and Address loading): 1. 2. 3. 4. 5. 6. 7. 25.7.
ATmega8U2/16U2/32U2 25.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 253 for details on Command and Data loading): 1. 2. 3. 4. 5. 25.7.10 A: Load Command “0100 0000”. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. Set BS2, BS1 to “01”. This selects high data byte. Give WR a negative pulse and wait for RDY/BSY to go high. Set BS2, BS1 to “00”. This selects low data byte.
ATmega8U2/16U2/32U2 25.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 253 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4.
ATmega8U2/16U2/32U2 25.8 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI (input) and PDO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 25-14 on page 259, the pin mapping for serial programming is listed.
ATmega8U2/16U2/32U2 25.9.1 Serial Programming Algorithm When writing serial data to the ATmega8U2/16U2/32U2, data is clocked on the rising edge of SCK. When reading data from the ATmega8U2/16U2/32U2, data is clocked on the falling edge of SCK. See Figure 25-8 for timing details. To program and verify the ATmega8U2/16U2/32U2 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 25-16): 1.
ATmega8U2/16U2/32U2 Table 25-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Figure 25-8.
ATmega8U2/16U2/32U2 Table 25-16. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0100 1101 0000 0000 cccc cccc xxxx xxxx Defines Extended Address Byte for Read Program Memory and Write Program Memory Page.
ATmega8U2/16U2/32U2 Table 25-16. Serial Programming Instruction Set (Continued) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. See Table 25-3 on page 247 for details. 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still busy.
ATmega8U2/16U2/32U2 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* Operating Temperature ................................. -55C to +125C *NOTICE: Storage Temperature..................................... -65°C to +150°C Voltage on any Pin except RESET & UVcc with respect to Ground(7) .............................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground .....-0.5V to +13.0V Voltage on UVcc with respect to Ground...........-0.5V to +6.
ATmega8U2/16U2/32U2 TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter RPUDP USB D+ Internal Pull-Up Power Supply Current(6) ICC Power-down mode Standby mode - 8MHZ XTAL Condition Min.(5) Max.(5) Units Idle mode 900 1500 Streaming mode 1425 3090 Typ. Active 8 MHz, VCC = 3V regulator disabled 4 6 mA Active 16 MHz, VCC = 5V regulator enabled 13.5 21 mA Idle 8 MHz, VCC = 3V regulator disabled 0.8 1.
ATmega8U2/16U2/32U2 5. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon 6. Values with “PRR1 – Power Reduction Register 1” disabled (0x00). 7.
ATmega8U2/16U2/32U2 26.4.3 External Clock Drive Table 26-2. External Clock Drive VCC=2.7-5.5V Symbol Parameter 1/tCLCL Min. Max. Min. Max. Units 0 8 0 16 MHz tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 s tCHCL Fall Time 1.6 0.5 s tCLCL Change in period from one clock cycle to the next 2 2 % Note: 26.5 Oscillator Frequency VCC=4.5-5.
ATmega8U2/16U2/32U2 Table 26-4. BODLEVEL Fuse Coding BODLEVEL 2..0 Fuses Min VBOT(1) 111 110 2.9 3.0 011 3.5 010 RESERVED 001 4.0 26.6 External Interrupts Characteristics tINT 2.7 100 1. The test is performed using BODLEVEL = 000 and 110. Symbol 2.5 RESERVED Note: Units BOD Disabled 101 000 Table 26-5. Max VBOT(1) Typ VBOT 4.1 V 4.3 4.
ATmega8U2/16U2/32U2 26.7 SPI Timing Characteristics See Figure 26-3 and Figure 26-7 for details. Table 26-6. SPI Timing Parameters Description Mode 1 SCK period Master See Table 17-5 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master TBD 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega8U2/16U2/32U2 Table 26-7. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 26.8 17 MSB ... LSB X Hardware Boot EntranceTiming Characteristics Figure 26-4. Hardware Boot Timing Requirements RESET tSHRH tHHRH ALE/HWB Table 26-8. 26.
ATmega8U2/16U2/32U2 Figure 26-6. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 26-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 26-7.
ATmega8U2/16U2/32U2 Table 26-9.
ATmega8U2/16U2/32U2 27. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
ATmega8U2/16U2/32U2 Figure 27-2. Active Supply Current vs. Frequency (Regulator Disabled T = 85°C) 8 3.6 V 7 3.3 V 6 3.0 V ICC (mA) 5 2.7 V 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Frequency (MHz) 27.2 Idle Supply Current Figure 27-3. Idle Supply Current vs. Frequency (Regulator Enabled T = 85°C) 4 5.5 V 3.5 5.0 V 3 4.5 V ICC (mA) 2.5 4.0 V 2 3.6 V 1.5 1 0.
ATmega8U2/16U2/32U2 Figure 27-4. Idle Supply Current vs. Frequency (Regulator Disabled T = 85°C 2.1 3.6 V 1.8 3.3 V 2.7 V ICC (mA) 1.5 1.2 0.9 0.6 0.3 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Frequency (MHz) 27.3 Power-down Supply Current Figure 27-5. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 6.8 85 °C 6.5 6.2 25 °C ICC (uA) 5.9 5.6 5.3 5 4.7 4.4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
ATmega8U2/16U2/32U2 Figure 27-6. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 16 85 °C 25 °C 15 14 ICC (uA) 13 12 11 10 9 8 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 27-7. Power-Down Supply Current vs. VCC (WDT Enabled BODEN) 43 85 °C 41 25 °C ICC (uA) 39 37 35 33 31 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.
ATmega8U2/16U2/32U2 27.4 Pin Pull-Up Figure 27-8. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) 150 125 IOP (uA) 100 75 50 -40 °C 25 °C 85 °C 25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 27-9. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V) 120 100 IRESET (uA) 80 60 40 25 °C -40 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega8U2/16U2/32U2 27.5 Pin Driver Strength Figure 27-10. I/O Pin Output Voltage vs. Sink Current(VCC = 3 V) 4 85 °C 3.5 3 VOL (V) 2.5 2 1.5 25 °C -40 °C 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 27-11. I/O Pin Output Voltage vs. Sink Current(VCC = 5 V) 0.9 0.8 85 °C 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.
ATmega8U2/16U2/32U2 Figure 27-12. I/O Pin Output Voltage vs. Source Current(Vcc = 3 V) 3.5 3 VOH (V) 2.5 2 -40 °C 1.5 25 °C 1 0.5 85 °C 0 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 27-13. I/O Pin Output Voltage vs. Source Current(VCC = 5 V) 5 4.9 4.8 VOH (V) 4.7 4.6 4.5 4.4 -40 °C 4.3 4.2 25 °C 4.
ATmega8U2/16U2/32U2 Figure 27-14. USB DP HI Pull-Up Resistor Current vs. USB Pin Voltage 1600 1400 1200 IUSB (uA) 1000 800 600 400 25 °C -40 °C 85 °C 200 0 0 0.5 1 1.5 2 2.5 3 3.5 VUSB (V) 27.6 Pin Threshold and Hysteresis Figure 27-15. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 1.7 -40 °C 25 °C 85 °C Threshold (V) 1.5 1.3 1.1 0.9 0.7 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
ATmega8U2/16U2/32U2 Figure 27-16. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 1.8 -40 °C 25 °C 85 °C Threshold (V) 1.6 1.4 1.2 1 0.8 0.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) 27.7 BOD Threshold Figure 27-17. BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V) 2.81 Rising Vcc 2.8 2.79 Threshold (V) 2.78 2.77 2.76 Falling Vcc 2.75 2.74 2.73 2.72 2.
ATmega8U2/16U2/32U2 Figure 27-18. BOD Thresholds vs. Temperature (BODLEVEL is 3.5 V) 3.58 Rising Vcc 3.57 Threshold (V) 3.56 Falling Vcc 3.55 3.54 3.53 3.52 3.51 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 Temperature (°C) Figure 27-19. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V) 4.39 Rising Vcc 4.38 Threshold (V) 4.37 Falling Vcc 4.36 4.35 4.34 4.33 4.32 4.
ATmega8U2/16U2/32U2 Figure 27-20. Bandgap Voltage vs. Vcc 1.107 Bandgap Voltage (V) 1.105 25 °C 1.103 85 °C 1.101 1.099 1.097 -40 °C 1.095 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 27.8 Internal Oscilllator Speed Figure 27-21. Watchdog Oscillator Frequency vs. Temperature 119 118 117 FRC (kHz) 116 115 114 1.9 V 113 2.7 V 112 3.6 V 111 5.
ATmega8U2/16U2/32U2 Figure 27-22. Watchdog Oscillator Frequency vs. VCC 119 118 117 -40 °C FRC (kHz) 116 115 25 °C 114 113 112 111 85 °C 110 109 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-23. Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.3 85 °C 8.2 FRC (MHz) 8.1 25 °C 8 7.9 -40 °C 7.8 7.7 2.5 3 3.5 4 4.5 5 5.
ATmega8U2/16U2/32U2 Figure 27-24. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 4.5 V 3.3 V 8.2 2.7 V FRC (MHz) 8.1 8 7.9 7.8 7.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 27-25. Calibrated 8 MHz RC Oscillator Frequency vs.
ATmega8U2/16U2/32U2 27.9 Current Consumption of Peripheral Units Figure 27-26. USB Regulator Level vs. VCC 3.4 25 °C 85 °C -40 °C Output Voltage (V) 3.3 3.2 3.1 3 2.9 2.8 3 3.5 4 4.5 5 5.5 Input Voltage (V) Figure 27-27. USB Regulator Level with load 75 vs. VCC 3.4 85 °C 25 °C -40 °C 3.2 Voltage (V) 3 2.8 2.6 2.4 2.2 2.5 3 3.5 4 4.5 5 5.
ATmega8U2/16U2/32U2 27.10 Current Consumption in Reset and Reset Pulsewidth Figure 27-28. Reset Supply Current vs. Frequency (Excluding Current Through the Reset Pullup) 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC (mA) 3 2.5 2 3.6 V 1.5 1 0.
ATmega8U2/16U2/32U2 28.
ATmega8U2/16U2/32U2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserved - - - - - - - - (0xBB) Reserved - - - - - - - - (0xBA) Reserved - - - - - - - - (0xB9) Reserved - - - - - - - - (0xB8) Reserved - - - - - - - - (0xB7) Reserved - - - - - - - - (0xB6) Reserved - - - - - - - - (0xB5) Reserved - - - - - - - - (
ATmega8U2/16U2/32U2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7C) Reserved - - - - - - - - (0x7B) Reserved - - - - - - - - (0x7A) Reserved - - - - - - - - (0x79) Reserved - - - - - - - - (0x78) Reserved - - - - - - - - (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) Reserved - - - - - - - - (
ATmega8U2/16U2/32U2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) Reserved - - - - - - - - 0x16 (0x36) TIFR1 - - ICF1 - OCF1C OCF1B OCF1A TOV1 page 136 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 page 107 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - - 0x
ATmega8U2/16U2/32U2 29.
ATmega8U2/16U2/32U2 Mnemonics Operands Description Operation Flags #Clocks ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..
ATmega8U2/16U2/32U2 30. Ordering Information 30.1 ATmega8U2 Speed Power Supply 16 MHz 2.7 - 5.5V Ordering Code Package ATmega8U2-AU 32A ATmega8U2-MU 32M1-A Operational Range -40C to +85C Package Type 32A 32-lead, 7 x7 x 1.2 mm, lead pitch 0.8 mm Thin Quad Flat Package 32M1 32-pad, 5 x 5 x 1 mm body, pad pitch 0.
ATmega8U2/16U2/32U2 30.2 ATmega16U2 Speed Power Supply 16 MHz 2.7 - 5.5V Ordering Code Package ATmega16U2-AU 32A ATmega16U2-MU 32M1-A Operational Range -40C to +85C Package Type 32A 32-lead, 7 x7 x 1.2 mm, lead pitch 0.8 mm Thin Quad Flat Package 32M1 32-pad, 5 x 5 x 1 mm body, pad pitch 0.
ATmega8U2/16U2/32U2 30.3 ATmega32U2 Speed Power Supply 16 MHz 2.7 - 5.5V Ordering Code Package ATmega32U2-AU 32A ATmega32U2-MU 32M1-A Operational Range -40C to +85C Package Type 32A 32-lead, 7 x7 x 1.2 mm, lead pitch 0.8 mm Thin Quad Flat Package 32M1 32-pad, 5 x 5 x 1 mm body, pad pitch 0.
ATmega8U2/16U2/32U2 31. Packaging Information 31.
ATmega8U2/16U2/32U2 31.
ATmega8U2/16U2/32U2 32. Errata 32.1 Errata ATmega8U2 The revision letter in this section refers to the revision of the ATmega8U2 device. 32.1.1 rev. A and rev B • Full Swing oscillator 1. Full Swing oscillator The maximum frequency for the Full Swing Crystal Oscillator is 8MHz. For Crystal frequencies > 8MHz the Full Swing Crystal Oscillator is not guaranteed to operate correctly.
ATmega8U2/16U2/32U2 32.3.2 rev. A and rev B • Full Swing oscillator 1. Full Swing oscillator The maximum frequency for the Full Swing Crystal Oscillator is 8MHz. For Crystal frequencies > 8MHz the Full Swing Crystal Oscillator is not guaranteed to operate correctly. Problem fix/Workaround If a Crystal with frequency > 8MHz is used, the Low Power Crystal Oscillator option should be used instead. See table 8-1 for an overview of the Device Clocking Options.
ATmega8U2/16U2/32U2 33. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 33.1 Rev.7799E – 09/12 1. 2. 33.2 Rev. 7799D – 11/10 1. 2. 3. 4. 5. 6. 7. 8. 33.3 Updated the footnote on page 2. Removed the VQFP from the footnote Updated Section 20-4 ”Typical Bus powered application with 3.3V I/O” on page 187. Updated Figure 20-6 on page 188.
ATmega8U2/16U2/32U2 33.5 Rev. 7799A – 03/09 1. Initial revision.
ATmega8U2/16U2/32U2 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Disclaimer ..................................................................................................................2 2 Overview ................................................................................................... 3 2.
8.8Clock Output Buffer .................................................................................................35 8.9System Clock Prescaler ..........................................................................................35 8.10PLL ........................................................................................................................36 8.11Register Description ..............................................................................................
ATmega8U2/16U2/32U2 14.1Overview ................................................................................................................88 14.2Internal Clock Source ............................................................................................88 14.3Prescaler Reset .....................................................................................................88 14.4External Clock Source ...........................................................................................
18.2Overview ..............................................................................................................148 18.3Clock Generation .................................................................................................149 18.4Frame Formats ....................................................................................................152 18.5USART Initialization .............................................................................................154 18.
ATmega8U2/16U2/32U2 21.4USB reset ............................................................................................................198 21.5Endpoint selection ...............................................................................................198 21.6Endpoint activation ..............................................................................................198 21.7Address Setup .....................................................................................................
25 Memory Programming ......................................................................... 246 25.1Program And Data Memory Lock Bits .................................................................246 25.2Fuse Bits ..............................................................................................................247 25.3Signature Bytes ...................................................................................................249 25.4Calibration Byte .................................
ATmega8U2/16U2/32U2 30.1ATmega8U2 ........................................................................................................294 30.2ATmega16U2 ......................................................................................................295 30.3ATmega32U2 ......................................................................................................296 31 Packaging Information ........................................................................ 297 31.1QFN32 ...............
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
