Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 44 (10x10) 8-Bit 8 MHz I/O number 32

Features

• High-performance, Low-power Atmel

AVR

8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 × 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 16 Kbytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1 Kbyte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• Operating Voltages

– 2.7V - 5.5V for ATmega16L

– 4.5V - 5.5V for ATmega16

• Speed Grades

– 0 - 8 MHz for ATmega16L

– 0 - 16 MHz for ATmega16

• Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L

– Active: 1.1 mA

– Idle Mode: 0.35 mA

– Power-down Mode: < 1 µA

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega16

ATmega16L

Summary

Rev. 2466TS–AVR–07/10

Summary of content (26 pages)

PAGE 1
Features • High-performance, Low-power Atmel® AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 16 Kbytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1 Kbyte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,
PAGE 2
Pin Configurations Figure 1.
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ATmega16(L) Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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ATmega16(L) Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention 6 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
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ATmega16(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $3F ($5F) SREG I T H S V N Z C 9 $3E ($5E) SPH – – – – – SP10 SP9 SP8 12 SP4 SP3 SP2 SP1 SP0 12 – – – IVSEL IVCE 48, 69 $3D ($5D) SPL $3C ($5C) OCR0 $3B ($5B) GICR SP7 SP6 SP5 Timer/Counter0 Output Compare Register INT1 INT0 Page 85 INT2 $3A ($5A) GIFR INTF1 INTF0 INTF2 – – – – – 70 $39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TO
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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $01 ($21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 181 $00 ($20) TWBR Notes: 8 Two-wire Serial Interface Bit Rate Register 180 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3.
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ATmega16(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two R
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Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd ← Rr Rd+1:Rd ← Rr+1:Rr LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
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ATmega16(L) Mnemonics Operands CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK Flags Description Operation Clear Half Carry Flag in SREG H←0 H No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr.
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Ordering Information Speed (MHz) Note: Power Supply Ordering Code Package 44A 40P6 44M1 Industrial (-40oC to 85oC) 44A 40P6 44M1 Industrial (-40oC to 85oC) 8 2.7V - 5.5V ATmega16L-8AU(1) ATmega16L-8PU(1) ATmega16L-8MU(1) 16 4.5V - 5.5V ATmega16-16AU(1) ATmega16-16PU(1) ATmega16-16MU(1) Operation Range 1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 44A 44-lead, Thin (1.
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ATmega16(L) Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
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40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C eB Notes: COMMON DIMENSIONS (Unit of Measure = mm) REF 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.
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ATmega16(L) 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig.
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Errata The revision letter in this section refers to the revision of the ATmega16 device. ATmega16(L) Rev. M • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1.
PAGE 17
ATmega16(L) Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronized to the asynchronous timer clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
PAGE 18
Problem Fix / Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx). 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.
PAGE 19
ATmega16(L) Problem Fix / Workaround – If ATmega16 is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.
PAGE 20
4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. ATmega16(L) Rev.
PAGE 21
ATmega16(L) Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Rev. 2466T-07/10 1. Corrected use of comma in formula Rp in Table 120, “Two-wire Serial Bus Requirements,” on page 294. 2. Updated document according to Atmel’s Technical Terminology 3. Note 6 and Note 7 under Table 120, “Two-wire Serial Bus Requirements,” on page 294 have been removed. Rev.
PAGE 22
Rev. 2466N-10/06 1. Updated “Timer/Counter Oscillator” on page 31. 2. Updated “Fast PWM Mode” on page 102. 3. Updated Table 38 on page 83, Table 40 on page 84, Table 45 on page 111, Table 47 on page 112, Table 50 on page 128 and Table 52 on page 129. 4. Updated C code example in “USART Initialization” on page 149. 5. Updated “Errata” on page 340. Rev. 2466M-04/06 1. Updated typos. 2. Updated “Serial Peripheral Interface – SPI” on page 135. 3.
PAGE 23
ATmega16(L) Rev. 2466G-10/03 1. Removed “Preliminary” from the datasheet. 2. Changed ICP to ICP1 in the datasheet. 3. Updated “JTAG Interface and On-chip Debug System” on page 36. 4. Updated assembly and C code examples in “Watchdog Timer Control Register – WDTCR” on page 43. 5. Updated Figure 46 on page 103. 6. Updated Table 15 on page 38, Table 82 on page 217 and Table 115 on page 276. 7. Updated “Test Access Port – TAP” on page 222 regarding JTAGEN. 8. Updated description for the JTD bit on page 231. 9.
PAGE 24
9. Added Table 73, “TWI Bit Rate Prescaler,” on page 182 to describe the TWPS bits in the “TWI Status Register – TWSR” on page 181. 10. Added section “Default Clock Source” on page 25. 11. Added note about frequency variation when using an external clock. Note added in “External Clock” on page 31. An extra row and a note added in Table 118 on page 293. 12. Various minor TWI corrections. 13. Added “Power Consumption” data in “Features” on page 1. 14.
PAGE 25
ATmega16(L) 8. Added JTAG version number for rev. H in Table 87 on page 229. 9. Added not regarding OCDEN Fuse below Table 105 on page 260. 10. Updated Programming Figures: Figure 127 on page 262 and Figure 136 on page 273 are updated to also reflect that AVCC must be connected during Programming mode. Figure 131 on page 269 added to illustrate how to program the fuses. 11. Added a note regarding usage of the “PROG_PAGELOAD ($6)” on page 280 and “PROG_PAGEREAD ($7)” on page 280. 12.
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