Datasheet

92
8024A–AVR–04/08
ATmega8HVA/16HVA
17.10.5 OCRnB – Timer/Counter n Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNTnL in 8-bit mode and TCNTnH in 16-bit mode). A match can be used to
generate an Output Compare interrupt.
In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing Reg-
isters in 16-bit Mode” on page 86.
Note that the OCRnB is not writable in Input Capture mode.
17.10.6 TIMSKn – Timer/Counter n Interrupt Mask Register
• Bit 3 – ICIEn: Timer/Counter n Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See Section “12.” on page 52.) is executed when the ICFn flag, located in TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Counter n Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCFnB bit is set in the ”TIFRn –
Timer/Counter n Interrupt Flag Register” on page 93.
• Bit 1 – OCIEnA: Timer/Counter n Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter n occurs, i.e., when the OCFnA bit is set in the ”TIFRn –
Timer/Counter n Interrupt Flag Register” on page 93.
• Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter n occurs, i.e., when the TOVn bit is set in the ”TIFRn – Timer/Counter
n Interrupt Flag Register” on page 93.
Bit 76543210
OCRnB[7:0] OCRnB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
----ICIEnOCIEnBOCIEnATOIEnTIMSKn
Read/Write R R R R R/W R/W R/W R
Initial Value00000000