Datasheet

90
8024A–AVR–04/08
ATmega8HVA/16HVA
17.10 Register Description
17.10.1 TCCRnA – Timer/Counter n Control Register A
• Bit 7– TCWn: Timer/Counter Width
When this bit is written to one 16-bit mode is selected. The Timer/Counter width is set to 16-bits
and the Output Compare Registers OCRnA and OCRnB are combined to form one 16-bit Output
Compare Register. Because the 16-bit registers TCNTnH/L and OCRnB/A are accessed by the
AVR CPU via the 8-bit data bus, special procedures must be followed. These procedures are
described in section ”Accessing Registers in 16-bit Mode” on page 86.
• Bit 6– ICENn: Input Capture Mode Enable
The Input Capture Mode is enabled when this bit is written to one.
• Bit 5 – ICNCn: Input Capture Noise Canceler
Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-
vated, the input from the Input Capture Source is filtered. The filter function requires four
successive equal valued samples of the Input Capture Source for changing its output. The Input
Capture is therefore delayed by four System Clock cycles when the noise canceler is enabled.
• Bit 4 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Source that is used to trigger a capture event.
When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the
ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is trig-
gered according to the ICESn setting, the counter value is copied into the Input Capture
Register. The event will also set the Input Capture Flag (ICFn), and this can be used to cause an
Input Capture Interrupt, if this interrupt is enabled.
• Bit 3 - ICSn: Input Capture Select
When written to a logic one, this bit selects the alternate Input Capture Source as trigger for the
Timer/Counter input capture function. To trigger the Timer/Counter Input Capture interrupt, the
ICIEn bit in the Timer Interrupt Mask Register (TIMSK) must be set. See Table 17-3 on page 84
and Table 17-4 on page 84.
• Bits 2:0 – Res: Reserved Bits
These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero.
• Bit 0 – WGMn0: Waveform Generation Mode
This bit controls the counting sequence of the counter, the source for maximum (TOP) counter
value, see Figure 17-6 on page 85. Modes of operation supported by the Timer/Counter unit are:
Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ”Timer/Counter
Timing Diagrams” on page 85).
Bit 76543210
TCWn ICENn ICNCn ICESn ICSn – – WGMn0 TCCRnA
Read/Write R/W R/W R/W R/W R/W R R R/W
Initial Value 0 0 0 0 0 0 0 0