Datasheet

86
8024A–AVR–04/08
ATmega8HVA/16HVA
Figure 17-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
clk_I/O
/8)
shows the setting of OCFnA and the clearing of TCNTn in CTC mode.
Figure 17-9. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f
clk_I/O
/8)
17.9 Accessing Registers in 16-bit Mode
In 16-bit mode (the TCWn bit is set to one) the TCNTnH/L and OCRnB/A are 16-bit registers that
can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte
accessed using two read or write operations. The 16-bit Timer/Counter has a single 8-bit register
for temporary storing of the high byte of the 16-bit access. The same temporary register is
shared between all 16-bit registers. Accessing the low byte triggers the 16-bit read or write oper-
ation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the
temporary register, and the low byte written, are both copied into the 16-bit register in the same
clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the low byte is read.
There is one exception in the temporary register usage. In the Output Compare mode the 16-bit
Output Compare Register OCRnB/A is read without the temporary register, because the Output
Compare Register contains a fixed value that is only changed by CPU access. However, in 16-
bit Input Capture mode the ICRn register formed by the OCRnA and OCRnB registers must be
accessed with the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
PCK
clk
Tn
(clk
PCK
/8)