Datasheet

8024A–AVR–04/08

ATmega8HVA/16HVA

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the trigger edge change is not required.

Note: 1. See ”OSI – Oscillator Sampling Interface” on page 28 for details.

17.7 Output Compare Unit

The comparator continuously compares the Timer/Counter (TCNTn) with the Output Compare

Registers (OCRnA and OCRnB), and whenever the Timer/Counter equals to the Output Com-

pare Registers, the comparator signals a match. A match will set the Output Compare Flag at

the next timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag

OCFnA or OCFnB, but in 16-bit mode the match can set only the Output Compare Flag OCFnA

as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output

Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automati-

cally cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by

writing a logical one to its I/O bit location. Figure 17-5 on page 84 shows a block diagram of the

Output Compare unit.

Figure 17-5. Output Compare Unit, Block Diagram

Table 17-3. Timer/Counter0 Input Capture Source (ICS)

ICS0 Source

0 ICP00: osi_posedge pin from OSI module

(1)

1 ICP01: Port PC0

Table 17-4. Timer/Counter1 Input Capture Source (ICS)

ICS1 Source

0 ICP10: Battery Protection Interrupt

1 ICP11: Voltage Regulator Interrupt

OCFn

x (Int.Req.)

= (8/16-bit Comparator )

OCRnx

DATA BUS

TCNTn