Datasheet

8024A–AVR–04/08

ATmega8HVA/16HVA

Figure 17-3. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCFnA Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care. If the new value written to

OCRnA is lower than the current value of TCNTn, the counter will miss the Compare Match. The

counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00

before the Compare Match can occur. As for the Normal mode of operation, the TOVn Flag is

set in the same timer clock cycle that the counter counts from MAX to 0x00.

17.5.3 16-bit Mode

In 16-bit mode, the counter (TCNTnH/L) is a incrementing until it overruns when it passes its

maximum 16-bit value (MAX = 0xFFFF) and then restarts from the bottom (0x0000), see Table

17-2 on page 80 for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock

cycle as the TCNTnH/L becomes zero. The TOVn Flag in this case behaves like a 17th bit,

except that it is only set, not cleared. However, combined with the timer overflow interrupt that

automatically clears the TOVn Flag, the timer resolution can be increased by software. There

are no special cases to consider in the Normal mode, a new counter value can be written any-

time. The Output Compare Unit can be used to generate interrupts at some given time.

17.5.4 Clear Timer on Compare Match (CTC) 16-bit Mode

In Clear Timer on Compare 16-bit mode, OCRnB/A Registers are used to manipulate the

counter resolution, see Table 17-2 on page 80 for bit settings. In CTC mode the counter is

cleared to zero when the counter value (TCNTn) matches OCRnB/A, where OCRnB represents

the eight most significant bits and OCRnA represents the eight least significant bits. OCRnB/A

defines the top value of the counter, hence also its resolution. This mode allows greater control

of the Compare Match output frequency. It also simplifies the operation of counting external

events.

An interrupt can be generated each time the counter reaches the TOP value by using the

OCFnA flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the

TOP value. However, changing the TOP to a value close the BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCRnB/A is lower than the current

value of TCNTn, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFFFF) and wrap around starting at 0x0000 before Compare Match can

occur. As for the 16-bit Mode, the TOVn Flag is set in the same timer clock cycle that the counter

counts from MAX to 0x0000.

CNTn

OCnx Interrupt Flag Set

1 4

eriod

2 3