Datasheet

79
8024A–AVR–04/08
ATmega8HVA/16HVA
17.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
17-2 on page 79 shows a block diagram of the counter and its surroundings.
Figure 17-2. Counter Unit Block Diagram
The counter is incremented at each timer clock (clk
Tn
) until it passes its TOP value and then
restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits
located in the Timer/Counter Control Register (TCCRnA). For more details about counting
sequences, see ”Timer/Counter Timing Diagrams” on page 85. clk
Tn
can be generated from an
external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock
source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, regardless of whether clk
Tn
is present or not. A CPU write overrides (has
priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOVn) is
set when the counter reaches the maximum value and it can be used for generating a CPU
interrupt.
Signal description (internal signals):
count Increment or decrement TCNTn by 1.
clk
Tn
Timer/Counter clock, referred to as clk
Tn
in the following.
top Signalize that TCNTn has reached maximum value.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn