Datasheet

8024A–AVR–04/08

ATmega8HVA/16HVA

15.3.2 Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 15-5.

The alternate pin configuration is as follows:

• MISO/INT2 - Port B, Bit 3

MISO, Master Data input: Slave Data output pin for SPI channel. When the SPI is enabled as a

Master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is

enabled as a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit. When not operat-

ing in SPI mode, this pin can serve as an external interrupt source.

• MOSI/INT1- Port B, Bit 2

MOSI, SPI Master Data output: Slave Data input for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit. When not operat-

ing in SPI mode, this pin can serve as an external interrupt source.

• SCK- Port B, Bit 1

SCK, Master Clock output: Slave Clock input pin for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit.

• SS/

CKOUT- Port B, Bit 0

, Slave Select input: When the SPI is enabled as a Slave, this pin is configured as an input

regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven low.

When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When

the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit.

When not operating in SPI mode, this pin can serve as Clock Output, CPU Clock divided by 2.

See ”Clock Output” on page 27.

Table 15-5. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB3 MISO/ INT2 (SPI Bus Master Input/Slave Output or External Interrupt 2 Input)

PB2 MOSI/ INT1 (SPI Bus Master Output/Slave Input or External Interrupt 1 Input)

PB1 SCK (SPI Bus Master clock Input)

PB0 SS/ CKOUT (SPI Bus Master Slave select or Clock Output)