Datasheet

59
8024A–AVR–04/08
ATmega8HVA/16HVA
14.2 High Voltage Ports as General Digital I/O
14.3 Overview
The high voltage ports are high voltage tolerant open collector output ports. In addition they can
be used as general digital inputs. Figure 14-2 shows a functional description of one output port
pin, here generically called Pxn.
Figure 14-2. General High Voltage Digital I/O
(1)
Note: 1. WRx, RRx and RPx are common to all pins within the same port. clk
I/O
and SLEEP are com-
mon to all ports.
14.3.1 Configuring the Pin
Each port pin consist of two register bits: PORTxn and PINxn. As shown in ”Register Descrip-
tion” on page 62, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits at
the PINx I/O address.
If PORTxn is written logic one, the port pin is driven low (zero). If PORTxn is written logic zero,
the port pin is tri-stated. The port pins are tri-stated when a reset condition becomes active, even
if no clocks are running.
14.3.2 Reading the Pin
The port pin can be read through the PINxn Register bit. As shown in Figure 14-2, the PINxn
Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metasta-
bility if the physical pin changes value near the edge of the internal clock, but it also introduces a
delay.
WRx
SLEEP: SLEEP CONTROL
clkI/O: I/O CLOCK
SLEEP
Pxn
Q D
Q
PORTxn
_
CLR
DATABU S
RRx
SYNCHRONIZER
QD
CLR
PINxn
clk
I/O
Q
_
D
L
Q
Q
SET
CLR
_
RESET
RPx
RRx: READ PORTx REGISTER
WRx: WRITE PORTx REGISTER
RPx: READ PINx REGISTER