Datasheet

49
8024A–AVR–04/08
ATmega8HVA/16HVA
11.4 Register Description
11.4.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bits 7:5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero.
Bit 4 – OCDRF: OCD Reset Flag
This bit is set if a debugWIRE Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 2 – BODRF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. This bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the reset flags.
11.4.2 WDTCSR – Watchdog Timer Control Register
Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
Bit 76543210
0x34 (0x54) OCDRF WDRF BODRF EXTRF PORF MCUSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
Bit 76543210
WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 X 0 0 0