Datasheet

44
8024A–AVR–04/08
ATmega8HVA/16HVA
5. When the internal reset goes low, software starts up and loads the VREF calibration reg-
isters to get VREF = 1.100V. As the VREF voltage changes, VREG voltage and VFET
DUVR voltage will rise proportionally to VREF.
Now the chip can operate normally, but writing to EEPROM in DUVR mode for single cell appli-
cations should be avoided.
11.2.2 External Reset
An External Reset is generated by a low level on the RESET
pin. Reset pulses longer than the
minimum pulse width (see Table 29-6 on page 170) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal
reaches the Reset Threshold Voltage – V
RST
– on its positive edge, the delay counter starts the
MCU after the Time-out period – t
TOUT
– has expired.
Figure 11-3. External Reset During Operation
11.2.3 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT
. Refer to
page 46 for details on operation of the Watchdog Timer.
Figure 11-4. Watchdog Reset During Operation
11.2.4 Brown-out Detection
ATmega8HVA/16HVA has an On-chip Brown-out Detection (BOD) circuit for monitoring the
V
REG
level during operation by comparing it to a fixed trigger level V
BOT
. The trigger level has a
hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level
should be interpreted as V
BOT+
= V
BOT
+ V
HYST
/2 and V
BOT-
= V
BOT
- V
HYST
/2.
CK
FET