Datasheet

43
8024A–AVR–04/08
ATmega8HVA/16HVA
Figure 11-2. Normal Start-up Sequence in Power-off.
1. The charger voltage pulls the BATT pin above the Power-on Threshold Voltage (V
POT
).
2. When V
BATT
rises above V
POT
, ATmega8HVA/16HVA turns on the Voltage Regulator and
VREG starts to rise. The POR reset will go high while VREG is rising and initiate the
internal reset state of the chip. The external FETs are initially switched off.
3. The internal reset is held high after POR reset goes low for a time given by t
TOUT
, see
”System Control and Reset” on page 41. While the chip is in reset, VREF calibration reg-
isters will be reset to their default values. The VREG and BOD levels are both referenced
to the VREF voltage. In reset all these voltage levels will therefore have default values.
Both FETs are switched completely off in this state.
4. As soon as the internal reset goes low, the chip will start operating in DUVR mode (for
details on DUVR mode, see ”DUVR – Deep Under-Voltage Recovery Mode operation”
on page 137 and application note AVR354). In DUVR mode the FET driver controls the
gate voltage of the Charge FET to get a voltage at the VFET pin given by the VFET level
specified in Table 29-5 on page 170. This causes the BATT voltage to decrease. Note
that DUVR mode will only regulate the VFET voltage as long as the cell voltage is lower
than the VFET_DUVR level. For high cell voltages, DUVR mode will not have any impact.
DUVR mode may be disabled by SW as soon as the chip enters ACTIVE mode.
Power-off
RESET
Active
O
per
ating Mode
POR Reset
Internal Reset
1
2
3
V
POT
5
4
VFET DUVR
VBATT
VREG
4/8/16/32/64/128/256/512 ms