Datasheet

39
8024A–AVR–04/08
ATmega8HVA/16HVA
10.8 Register Description
10.8.1 SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero.
• Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0
These bits select between the four available sleep modes as shown in Table 10-3.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
10.8.2 PRR0 – Power Reduction Register 0
• Bit 7:6, 4 - Res: Reserved bits
These bits are reserved for future use. For compatibility with future devices, these bits must be
written to zero when PRR0 is written.
• Bit 5 - PRVRM: Power Reduction Voltage Regulator Monitor
Writing a logic one to this bit shuts down the Voltage Regulator Monitor interface by stopping the
clock of the module.
Bit 76543210
0x33 (0x53) – – – – SM2 SM1 SM0 SE SMCR
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
Table 10-3. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
000Idle
0 0 1 ADC Noise Reduction
010Reserved
011Power-save
100Power-off
101Reserved
110Reserved
111Reserved
Bit 7 6 5 4 3 2 1 0
(0x64) – – PRVRM – PRSPI PRTIM1 PRTIM0 PRVADC PRR0
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0