Datasheet

33
8024A–AVR–04/08
ATmega8HVA/16HVA
• Bit 4 - OSISEL0: Oscillator Sampling Interface Select 0
• Bit 1 – OSIST: Oscillator Sampling Interface Status
This bit continuously displays the phase of the prescaled clock. This bit can be polled by the
CPU to determine the rising and falling edges of the prescaled clock.
• Bit 0 – OSIEN: Oscillator Sampling Interface Enable
Setting this bit enables the Oscillator Sampling Interface. When this bit is cleared, the Oscillator
Sampling Interface is disabled.
Notes: 1. The prescaler is reset each time the OSICSR register is written, and hence each time a new
oscillator source is selected.
Table 9-5. OSISEL Bit Description
OSISEL0 Oscillator source
0 ULP Oscillator
1 Slow RC Oscillator